JP5043682B2 - 反比例するプロセス依存参照電流を使用してスルーレート制御する出力バッファ - Google Patents
反比例するプロセス依存参照電流を使用してスルーレート制御する出力バッファ Download PDFInfo
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- JP5043682B2 JP5043682B2 JP2007552213A JP2007552213A JP5043682B2 JP 5043682 B2 JP5043682 B2 JP 5043682B2 JP 2007552213 A JP2007552213 A JP 2007552213A JP 2007552213 A JP2007552213 A JP 2007552213A JP 5043682 B2 JP5043682 B2 JP 5043682B2
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- 230000008569 process Effects 0.000 title claims description 35
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018557—Coupling arrangements; Impedance matching circuits
- H03K19/018571—Coupling arrangements; Impedance matching circuits of complementary type, e.g. CMOS
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
- Electronic Switches (AREA)
- Amplifiers (AREA)
Description
スルーレート制御を行う1つの手法としては、出力スルーレートを正確に示す出力バッファの複製回路を構築することが挙げられる。
次に、スルーレート制御電流は、複製スルーレートの測定値が範囲内になるまで調整される。
Iout=(VIO/2)×(1/REXT)×(1/N)=VIO/4000
である。
なお、Cは定数である。
Avが大きい場合、入力がゲートの増幅器のしきい値に到達する前のスルーレートは、
であり、nIREFは電流源510により供給される電流である。出力スルーの間、
である。
Claims (8)
- 集積回路の出力ドライバー回路の出力のスルーレートの変動を低減する方法であって、
前記出力ドライバー回路の第1トランジスタのゲートに接続されたノードに集積回路パフォーマンスに反比例する一定の大きさを有する第1電流を供給するステップと、
前記出力ドライバー回路が安定な出力値に達するように、前記第1トランジスタの前記ゲートに接続された前記ノードにフィードバック回路を介して付加的な電流(855)を供給するステップとを含み、前記安定な出力値が、第1及び第2の出力供給ノードの各々1つに対応し、前記付加的な電流が、前記出力ドライバーでの信号の値に基づいている方法。 - さらに、前記出力ドライバー回路の第2トランジスタのゲートに接続されたノードに、パフォーマンスに反比例する一定の大きさを有する第2入力電流を供給することによりスルーレートの変動を低減するステップを含む請求項1に記載の方法。
- 第1の値を有する入力ノード上のデータに応答して、前記第1トランジスタが、前記出力ドライバー回路の出力を第1電源ノードに接続し、
第2の値を有する前記入力ノード上のデータに応答して、前記第2トランジスタが前記出力ドライバー回路の出力を第2電源ノードに接続する請求項2に記載の方法。 - 前記第1電流が、参照電流と、パフォーマンスに直接関連する第2電流とを用いて生成される請求項1に記載の方法。
- 出力回路と1または2以上の付加的なトランジスタ(855)とを備えた集積回路であって、
前記出力回路は、第1の値を有する入力ノード上のデータに応答して、前記集積回路の出力端子(869)を第1電源ノードに接続する第1トランジスタ(817)を含み、該第1トランジスタのゲートが、前記出力回路のパフォーマンスに反比例する第1電流を受け取るように構成された第1のノード(860)に接続されており、
該第1のノードに接続された前記付加的なトランジスタ(855)が、前記出力回路の信号が所与の出力値に達したときに、前記第1のノードに付加的な電流を提供するように構成されている集積回路。 - 前記出力回路が、さらに第2トランジスタを備え、
該第2トランジスタのゲートが、前記出力回路のパフォーマンスに反比例する第2電流を受け取るように構成された第2のノードに接続され、
前記データが第2の値にあるときに、前記第2トランジスタが第2電源ノードに前記出力端子を接続する請求項5に記載の集積回路。 - プロセス依存電流を供給する第1電流源と、参照電流を供給する第2電流源とをさらに備え、前記第1のノード(860)を通る電流が前記プロセス依存電流と前記参照電流とを組み合わせることによって形成される請求項5に記載の集積回路。
- 外部抵抗と前記集積回路の出力端子における電圧とによって決まる電流の値に比例した前記参照電流に対応する電流を生成する電流ミラーをさらに備えた請求項7に記載の集積回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/038,909 | 2005-01-20 | ||
US11/038,909 US7521975B2 (en) | 2005-01-20 | 2005-01-20 | Output buffer with slew rate control utilizing an inverse process dependent current reference |
PCT/US2006/001595 WO2006078649A1 (en) | 2005-01-20 | 2006-01-17 | Output buffer with slew rate control utilizing an inverse process dependent current reference |
Publications (2)
Publication Number | Publication Date |
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JP2008529358A JP2008529358A (ja) | 2008-07-31 |
JP5043682B2 true JP5043682B2 (ja) | 2012-10-10 |
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JP2007552213A Active JP5043682B2 (ja) | 2005-01-20 | 2006-01-17 | 反比例するプロセス依存参照電流を使用してスルーレート制御する出力バッファ |
Country Status (8)
Country | Link |
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US (1) | US7521975B2 (ja) |
JP (1) | JP5043682B2 (ja) |
KR (1) | KR101196871B1 (ja) |
CN (1) | CN101107779B (ja) |
DE (1) | DE112006000251B4 (ja) |
GB (1) | GB2438104B (ja) |
TW (1) | TWI377790B (ja) |
WO (1) | WO2006078649A1 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7991369B2 (en) * | 2006-09-26 | 2011-08-02 | Silicon Laboratories Inc. | Reducing power dissipation using process corner information |
US7902885B2 (en) * | 2006-12-28 | 2011-03-08 | Stmicroelectronics Pvt. Ltd. | Compensated output buffer for improving slew control rate |
CN101325362B (zh) * | 2008-04-15 | 2010-07-21 | 福州大学 | 无短路损耗的cmos缓冲器驱动电路 |
US7911262B2 (en) * | 2009-03-29 | 2011-03-22 | Nanya Technology Corp. | External compensation for input current source |
US9176558B2 (en) * | 2009-09-29 | 2015-11-03 | Silicon Laboratories Inc. | Optimizing bias points for a semiconductor device |
US8154322B2 (en) * | 2009-12-21 | 2012-04-10 | Analog Devices, Inc. | Apparatus and method for HDMI transmission |
US7928769B1 (en) * | 2010-03-25 | 2011-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Logic circuits with current control mechanisms |
US8344793B2 (en) * | 2011-01-06 | 2013-01-01 | Rf Micro Devices, Inc. | Method of generating multiple current sources from a single reference resistor |
US8736357B2 (en) | 2011-02-28 | 2014-05-27 | Rf Micro Devices, Inc. | Method of generating multiple current sources from a single reference resistor |
US8508304B2 (en) * | 2011-10-17 | 2013-08-13 | Texas Instruments Incorporated | Serdes VCO with phased outputs driving frequency to voltage converter |
US8922254B2 (en) * | 2013-01-29 | 2014-12-30 | Macronix International Co., Ltd. | Drive circuitry compensated for manufacturing and environmental variation |
US9444462B2 (en) | 2014-08-13 | 2016-09-13 | Macronix International Co., Ltd. | Stabilization of output timing delay |
US9419596B2 (en) | 2014-09-05 | 2016-08-16 | Macronix International Co., Ltd. | Sense amplifier with improved margin |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5311077A (en) * | 1992-07-15 | 1994-05-10 | National Semiconductor Corporation | Power supply, temperature, and load capacitance compensating, controlled slew rate output buffer |
EP0678983B1 (en) | 1994-04-22 | 1998-08-26 | STMicroelectronics S.r.l. | Output buffer current slew rate control integrated circuit |
US5568084A (en) * | 1994-12-16 | 1996-10-22 | Sgs-Thomson Microelectronics, Inc. | Circuit for providing a compensated bias voltage |
US5510729A (en) * | 1995-03-27 | 1996-04-23 | General Datacomm, Inc. | Output characteristics stabilization of CMOS devices |
EP0765037A3 (en) * | 1995-09-20 | 1998-01-14 | Texas Instruments Incorporated | Buffer for integrated circuit memories |
US5877647A (en) * | 1995-10-16 | 1999-03-02 | Texas Instruments Incorporated | CMOS output buffer with slew rate control |
EP0782269B1 (en) * | 1995-12-26 | 2002-06-05 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
US5633603A (en) * | 1995-12-26 | 1997-05-27 | Hyundai Electronics Industries Co., Ltd. | Data output buffer using pass transistors biased with a reference voltage and a precharged data input |
US5973512A (en) * | 1997-12-02 | 1999-10-26 | National Semiconductor Corporation | CMOS output buffer having load independent slewing |
US6243426B1 (en) * | 1998-09-30 | 2001-06-05 | Advanced Micro Devices, Inc. | Apparatus and method for slew rate control of MLT-3 transmitter using zero drive |
EP1091492A1 (en) * | 1999-10-08 | 2001-04-11 | STMicroelectronics S.r.l. | An output buffer for digital signals |
US6445170B1 (en) * | 2000-10-24 | 2002-09-03 | Intel Corporation | Current source with internal variable resistance and control loop for reduced process sensitivity |
EP1237279A1 (en) | 2001-02-21 | 2002-09-04 | STMicroelectronics S.r.l. | Output buffer with automatic control of the switching speed as a function of the supply voltage and temperature |
US6437622B1 (en) * | 2001-03-27 | 2002-08-20 | Texas Instruments Incorporated | Temperature compensated slew rate control circuit |
US6606271B2 (en) * | 2001-05-23 | 2003-08-12 | Mircron Technology, Inc. | Circuit having a controllable slew rate |
JP4675008B2 (ja) * | 2001-09-17 | 2011-04-20 | ルネサスエレクトロニクス株式会社 | 半導体回路装置 |
JP3532181B2 (ja) * | 2001-11-21 | 2004-05-31 | 沖電気工業株式会社 | 電圧トランスレータ |
US7019551B1 (en) * | 2001-12-27 | 2006-03-28 | Advanced Micro Devices, Inc. | Output buffer with slew rate control and a selection circuit |
US6690192B1 (en) * | 2002-10-16 | 2004-02-10 | Pericom Semiconductor Corp. | Current-compensated CMOS output buffer adjusting edge rate for process, temperature, and Vcc variations |
US6903588B2 (en) * | 2003-04-15 | 2005-06-07 | Broadcom Corporation | Slew rate controlled output buffer |
US7154309B1 (en) * | 2005-01-13 | 2006-12-26 | Advanced Micro Devices, Inc. | Dual-mode output driver configured for outputting a signal according to either a selected high voltage/low speed mode or a low voltage/high speed mode |
-
2005
- 2005-01-20 US US11/038,909 patent/US7521975B2/en active Active
-
2006
- 2006-01-17 TW TW095101679A patent/TWI377790B/zh active
- 2006-01-17 CN CN2006800027402A patent/CN101107779B/zh active Active
- 2006-01-17 WO PCT/US2006/001595 patent/WO2006078649A1/en active Application Filing
- 2006-01-17 KR KR1020077016417A patent/KR101196871B1/ko active IP Right Grant
- 2006-01-17 DE DE112006000251.1T patent/DE112006000251B4/de active Active
- 2006-01-17 JP JP2007552213A patent/JP5043682B2/ja active Active
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Also Published As
Publication number | Publication date |
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CN101107779A (zh) | 2008-01-16 |
KR20070095954A (ko) | 2007-10-01 |
DE112006000251T5 (de) | 2008-02-07 |
JP2008529358A (ja) | 2008-07-31 |
TW200642270A (en) | 2006-12-01 |
DE112006000251B4 (de) | 2017-11-02 |
GB2438104B (en) | 2009-12-02 |
US20060190880A1 (en) | 2006-08-24 |
US7521975B2 (en) | 2009-04-21 |
WO2006078649A1 (en) | 2006-07-27 |
GB2438104A (en) | 2007-11-14 |
TWI377790B (en) | 2012-11-21 |
CN101107779B (zh) | 2010-10-27 |
GB0713747D0 (en) | 2007-08-22 |
KR101196871B1 (ko) | 2012-11-01 |
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