JP2008511973A - パワー半導体デバイス - Google Patents
パワー半導体デバイス Download PDFInfo
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- JP2008511973A JP2008511973A JP2007528616A JP2007528616A JP2008511973A JP 2008511973 A JP2008511973 A JP 2008511973A JP 2007528616 A JP2007528616 A JP 2007528616A JP 2007528616 A JP2007528616 A JP 2007528616A JP 2008511973 A JP2008511973 A JP 2008511973A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims 1
- 230000001737 promoting effect Effects 0.000 claims 1
- 238000003491 array Methods 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 description 19
- 239000002019 doping agent Substances 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 7
- 239000007943 implant Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 210000000746 body region Anatomy 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
Abstract
Description
36 併合ベース領域
37 ソース領域
63 第1の基板層
76 ゲート酸化物層
78 追加層
83 ドレイン電極
102 浮遊電圧領域
106 アイランド又はプラグ
112 追加層
Claims (7)
- 基板(62)の表面上に分配されたセルのアレイを備えるパワー半導体デバイスであって、各セルが、
前記基板表面に形成されたソース領域(37)と、
前記基板内で前記ソース領域を囲むベース領域(36)と、
前記ベース領域を囲むドレイン領域と、
前記ドレイン領域に接触するドレイン電極(83)と、
を有し、
前記アレイの個々のセルの前記ソース領域(37)が、隣接セルの少なくとも1つのソース領域分岐部(80)に向かって横方向外側に各々が延びた複数のソース領域分岐部(80)を備え、前記隣接セルのソース領域分岐部が並置端部を提供し、前記アレイの個々のセルの前記ベース領域(36)が、前記隣接セルの少なくとも1つのベース領域に向かって横方向に各々が延びた対応する複数のベース領域分岐部を備え、前記隣接セルのベース領域分岐部が前記並置端部間に隣接して共に併合されて前記基板内の前記アレイの個々のセルのソース領域(37)を囲む単一のベース領域を形成し、横方向で前記併合ベース領域(36)と前記ドレイン領域との間の凹面だけである接合部が隣接するセル間の前記デバイスのオン状態において円形電流伝導経路域(39)を定め、該導電経路が前記デバイスのオフ状態では消失して前記ソース領域(37)から前記ドレイン電極(83)への電流フローが阻止されるパワー半導体デバイスにおいて、
前記ドレイン領域に対して逆の導電型の浮遊電圧領域(102)が、前記併合ベース領域(36)の下方で前記基板(62)に埋め込まれ、且つ各セル内で前記併合ベース領域(36)の特徴部に対応しこれに並置される特徴部(104)を提供し、その結果、前記電流伝導経路を阻止する空乏層が前記浮遊電圧領域(102)に到達すると、前記浮遊電圧領域(102)の電圧が前記ソース領域(37)の電圧に向かい、これによって前記空乏層の成長が促進されることを特徴とするパワー半導体デバイス。 - 前記浮遊電圧領域の特徴部(104)が、それぞれのセルの前記電流伝導経路(39)を囲む、前記ドレイン領域に対して逆の導電型リングを定めることを特徴とする請求項1に記載のパワー半導体デバイス。
- 隣接セルの前記浮遊電圧領域(102)の特徴部(104)が共に併合することを特徴とする請求項2に記載のパワー半導体デバイス。
- 前記浮遊電圧領域(102)が、前記電流伝導経路(39)内部に位置するそれぞれのアイランド(106)を含むことを特徴とする前記請求項の何れかに記載のパワー半導体デバイス。
- 前記浮遊電圧領域(102)が、前記基板の2つの層(108、110)の間の境界面に隣接して延びることを特徴とする前記請求項の何れかに記載のパワー半導体デバイス。
- 前記電流伝導経路(39)の各々が、前記2つの層(108、110)よりも低濃度にドープされ且つ前記2つの層と同じ導電型である追加層(112)を前記境界面に隣接して含むことを特徴とする請求項5に記載のパワー半導体デバイス。
- 前記2つの層(108、110)が、前記層の順次的エピタキシャル成長を含む工程によって形成されることを特徴とする請求項5又は請求項6に記載のパワー半導体デバイス。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2004/011074 WO2006024322A1 (en) | 2004-08-31 | 2004-08-31 | Power semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008511973A true JP2008511973A (ja) | 2008-04-17 |
JP4990140B2 JP4990140B2 (ja) | 2012-08-01 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007528616A Expired - Fee Related JP4990140B2 (ja) | 2004-08-31 | 2004-08-31 | パワー半導体デバイス |
Country Status (4)
Country | Link |
---|---|
US (1) | US8004049B2 (ja) |
EP (1) | EP1790013A1 (ja) |
JP (1) | JP4990140B2 (ja) |
WO (1) | WO2006024322A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101367491B1 (ko) | 2012-08-08 | 2014-02-26 | 고려대학교 산학협력단 | 단일 fli 구조를 갖는 반도체 소자의 제조 방법 및 그 제조 방법으로 제조된 반도체 소자 |
Families Citing this family (12)
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US8779465B2 (en) | 2006-09-22 | 2014-07-15 | Freescale Semiconductor, Inc. | Semiconductor device and method of forming a semiconductor device |
US7955929B2 (en) * | 2007-01-10 | 2011-06-07 | Freescale Semiconductor, Inc. | Method of forming a semiconductor device having an active area and a termination area |
WO2008099229A1 (en) * | 2007-02-14 | 2008-08-21 | Freescale Semiconductor, Inc. | Semiconductor device and method of forming a semiconductor device |
US8743626B2 (en) * | 2011-02-18 | 2014-06-03 | Synopsys, Inc. | Controlling a non-volatile memory |
US8829609B2 (en) * | 2011-07-28 | 2014-09-09 | Stmicroelectronics S.R.L. | Insulated gate semiconductor device with optimized breakdown voltage, and manufacturing method thereof |
US8907483B2 (en) | 2012-10-10 | 2014-12-09 | Globalfoundries Inc. | Semiconductor device having a self-forming barrier layer at via bottom |
EP2884538A1 (en) | 2013-12-16 | 2015-06-17 | ABB Technology AB | Power semiconductor device |
US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
EP3183754A4 (en) | 2014-08-19 | 2018-05-02 | Vishay-Siliconix | Super-junction metal oxide semiconductor field effect transistor |
US10096681B2 (en) * | 2016-05-23 | 2018-10-09 | General Electric Company | Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) device cells |
JP7024238B2 (ja) * | 2017-07-25 | 2022-02-24 | 日本電産リード株式会社 | 接続モジュール、検査治具、及び基板検査装置 |
CN117690968A (zh) * | 2024-02-02 | 2024-03-12 | 深圳天狼芯半导体有限公司 | 一种mos管及其制备方法 |
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2004
- 2004-08-31 JP JP2007528616A patent/JP4990140B2/ja not_active Expired - Fee Related
- 2004-08-31 EP EP04765803A patent/EP1790013A1/en not_active Withdrawn
- 2004-08-31 US US11/574,478 patent/US8004049B2/en active Active
- 2004-08-31 WO PCT/EP2004/011074 patent/WO2006024322A1/en active Application Filing
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WO2003030244A1 (en) * | 2001-10-04 | 2003-04-10 | General Semiconductor, Inc. | Method for fabricating a power semiconductor device having a floating island voltage sustaining layer |
JP2005505921A (ja) * | 2001-10-04 | 2005-02-24 | ゼネラル セミコンダクター,インク. | フローティングアイランド電圧維持層を有する半導体パワーデバイス |
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KR101367491B1 (ko) | 2012-08-08 | 2014-02-26 | 고려대학교 산학협력단 | 단일 fli 구조를 갖는 반도체 소자의 제조 방법 및 그 제조 방법으로 제조된 반도체 소자 |
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US8004049B2 (en) | 2011-08-23 |
WO2006024322A1 (en) | 2006-03-09 |
US20090014792A1 (en) | 2009-01-15 |
JP4990140B2 (ja) | 2012-08-01 |
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