WO2006059300A2 - Insulated gate field effect transistors - Google Patents

Insulated gate field effect transistors Download PDF

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Publication number
WO2006059300A2
WO2006059300A2 PCT/IB2005/053994 IB2005053994W WO2006059300A2 WO 2006059300 A2 WO2006059300 A2 WO 2006059300A2 IB 2005053994 W IB2005053994 W IB 2005053994W WO 2006059300 A2 WO2006059300 A2 WO 2006059300A2
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Prior art keywords
cells
active
inactive
field effect
effect transistor
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PCT/IB2005/053994
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French (fr)
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WO2006059300A3 (en
Inventor
Adam Brown
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Koninklijke Philips Electronics N.V.
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Priority to EP05821637A priority Critical patent/EP1820217A2/en
Priority to JP2007543983A priority patent/JP2008523586A/en
Publication of WO2006059300A2 publication Critical patent/WO2006059300A2/en
Publication of WO2006059300A3 publication Critical patent/WO2006059300A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Definitions

  • the invention relates to insulated gate field effect transistors and methods of using them.
  • MOSFETs Power metal oxide semiconductor field effect transistors
  • MOSFETs are generally used as switches in which they are either fully on or fully off.
  • MOSFETs can also be used in a linear region of operation to self- protect the MOSFET from over-voltage spikes by turning on and absorbing power as part of a linear region of operation, typically using a dynamic current circuit, or to limit the current for a short period of time long enough for a decision to be made to switch the current to a safe state.
  • Other circuits also require operation in the linear mode. For example, many simple motors are controlled in this way, such as fan motors.
  • the reason for the thermal runaway in small devices is the existence of a critical current density J c above which the current density decreases with increasing temperature but below which the current density increases with increasing temperature. If a FET is operated below the critical current density J c a small increase in temperature increases current density, which causes an increase in temperature, causing still higher current density, i.e. thermal runaway.
  • the value of the critical current density J c is determined by two competing effects. Firstly, as temperature increases the resistance of the channel increases. This decreases current density with increasing temperature. Secondly, as temperature increases, the threshold voltage of the MOSFET decreases. This change in threshold voltage does not matter when the MOSFET is switched hard on. However, in the linear regime, the decreased threshold voltage changes the effective gate voltage thereby increasing current density with increasing temperature. As the gain increases, the second effect becomes relatively more important. Modern MOSFETs have high values of gate width per unit area and are operated at currents such that the second effect is dominant, i.e. the MOSFETs are operated below J c .
  • the problem is not limited to devices using oxide on silicon, but can occur in any power FET.
  • an insulated gate field effect transistor according to claim 1.
  • the operation of the device in the linear regime is enhanced.
  • the inventors have realised that it is not necessary to provide multiple different threshold voltages or cells that have asymmetric channels or complex forms. All that is required is that some of the cells are used and others are unused.
  • the current may be uniformly spread over the device avoiding hot spots by virtue of the fact that the active cells are not crowded together.
  • the active cells are evenly distributed amongst the inactive cells.
  • a real benefit of the invention is that improved linear performance is obtained in an arrangement that is very easy to manufacture.
  • the invention is implemented as a vertical transistor, wherein the gate is an insulated gate extending into the substrate from the first major surface.
  • the cells may include a body region of the FET, with an insulated gate in trenches between the cells. Source regions may be provided only in the active cells.
  • the cells may be arranged in a hexagonal array, and the ratio of active cells to inactive cells may be 1 :2. This is easy to arrange in a hexagonal array and provides enough active cells to pass current with the device turned on.
  • the cell pitch may be less than 1 1 ⁇ m.
  • the invention is particularly applicable to devices with such small cell pitches, for which the zero temperature coefficient current may be particularly high and hence for which thermal instability is a particular problem.
  • the ratio of active cells to inactive cells may be 1 :2. This is a convenient ratio which gives good results for moderate cell pitches.
  • the invention includes devices wherein the cell pitch is 8 ⁇ m or less and the fraction of the number of active cells divided by the number of inactive cells has a value 1/3 or less.
  • the step of defining the transistor may include: etching a trench extending into the substrate from the first major surface between the cells; depositing gate insulator on the sidewalls and base of the trench; and filling the trench with gate conductor.
  • the step of defining the transistor may further include: implanting a p-type body to form the cells; and after defining the trenches, implanting source regions adjacent to the trenches in the active cells but not the inactive cells.
  • Figure 1 shows a side view of an active cell and an inactive cell as used in the first embodiment of the invention
  • Figure 2 shows a top view of a semiconductor device according to the first embodiment of the invention
  • Figure 3 shows graphs of current against voltage at different temperatures for the first embodiment and a comparative example using only active cells
  • Figure 4 shows pass and fail values of current and voltage for devices according to the invention and a comparative example
  • Figure 5 shows a top view of a semiconductor device of an alternative embodiment of the invention.
  • a doped n+ semiconductor substrate 2 functions as the drain for a semiconductor device made up of a number of cells 6 at a first, top, major surface 4 of the substrate.
  • the cells are divided into active cells 8 and inactive cells 10.
  • the substrate may for example be a commercially available silicon substrate with a doping concentration in the range 10 15 cm “3 to 10 18 cm “3 . Alternative materials and doping may be used if required.
  • a p-doped body region 12 is provided in each of the active cells 8 and the inactive cells 10.
  • the cells 6 are separated by insulated gate trenches 14 which have a gate insulator 16 on the sidewalls and base of the trench and a conductor 18 within the trench to act as a gate.
  • the cells 6 are distributed over the first major surface 4 of the substrate in a hexagonal array with the insulated gate trenches 14 connecting up so that the gate conductor 18 is linked.
  • the active cells 8 differ from the inactive cells 10 in that the active cells further comprise heavily doped n+ source regions 20 at the first major surface 4 in the body region 12, whereas these are omitted from the inactive cells 10.
  • An insulator 22 is arranged over the trenches 14 and partially over the source regions 20 to insulate the trench.
  • the source region may for example be a ring shape leaving the centre of the ring as part of the body region 12.
  • a metallisation layer 24 then extends over the surface of the insulator
  • the trench has a similar width to depth in the range 1 ⁇ m to 3 ⁇ m. As will be appreciated, the trench depth and width can be varied depending on the device properties required.
  • a back contact 28 is provided on the rear of the substrate 2 and a gate contact 30 is connected to the gate conductor 18.
  • the gate insulator 16 may be made of any convenient material, including for example silicon oxide, silicon nitride and silicon oxynitride. Multiple layer gates may also be used if required.
  • the active cells 8 are distributed over the surface of the substrate as illustrated in Figure 2 in which the active cells 8 are shaded to distinguish them from the inactive cells 10. It will be seen that the pattern in this embodiment is a repeating pattern of two inactive cells 10 and one active cell 8, as indicated by the triangle 26, and so the ratio of inactive to active cells is 2:1.
  • the cell pitch that is to say the distance between the centres of adjacent cells, in this embodiment is 9 ⁇ m.
  • the device may be manufactured in a relatively conventional process which will accordingly not be described further. However, one modification is required so that the source diffusion is not carried out in the inactive cells. This is carried out by creating a mask pattern that covers the centre of the cell for the active cells, and covers the whole cell for the inactive cells, before carrying out an implantation step to implant the heavily doped n+ source regions 20 in the body region 12. In this way, the source regions 20 are created only in the active cells.
  • the current- voltage characteristic is shown in Figure 3 at two temperatures.
  • the leftmost two curves relate to the comparative example and the rightmost two curves to the embodiment.
  • the two temperatures were 25 -C and 175 -C for each case.
  • the zero temperature coefficient point is the current at which the same voltage is required to produce the current at different temperatures, i.e. the current at which the curves cross.
  • the zero temperature coefficient point dropped from about 8OA in the comparative example to about 35A in the embodiment. Good yields of devices were obtained.
  • Figure 4 shows some failure points, i.e. values of current and voltage that when applied for a predetermined period caused failure. In some cases, a 100ms period was used, and in others a dc signal. 100ms failure points of the embodiment are labelled 32, at higher current values than the failure points of the comparative example 34. At dc, pass points of the embodiment, labelled 36, occur at very similar values to failure points 38 of the comparative example.
  • Typical Rdson (resistance in the on state) values were 9 mOhm for the embodiment and 5.4mOhm for the comparative example. Since in the embodiment only one third of the cells are active this is a good result.
  • the embodiment has cells that are the bodies of the transistors, surrounded by trenches. It is also possible to arrange the cells to be the trenches of the transistors, and the p-type bodies as the trench.
  • the active cells may be provided by providing gate contacts only for the active cells and leaving the inactive cells with floating gates.
  • the cells need not be hexagonal, but may be square, triangular, or any other suitable shape. Indeed, not all cells need to be the same. Such shapes and arrangements are taught in US 6,320,223 and the various cell variations taught therein are expressly included by reference.
  • the first major surface may be divided into stripes 50, the active cells 8 being short regions of the stripes 50, the remainder of the stripes constituting an inactive cell 10. As may be seen in Figure 5, some stripes constitute only an inactive cell 10. Alternatively, all stripes may have active and inactive cells, for example by offsetting the active cells in adjacent stripes. Note that in these embodiments the cell size of the inactive cells 10 is greater than that of the active cells 8.
  • An alternative arrangement using stripes has cells in the form of stripes arranged in parallel, the whole length of the stripe being either active or inactive.
  • the active cell stripes (acting as a transistor) are interdispersed between inactive cell stripes.
  • the cell pitch need not be the 9 ⁇ m of the embodiment.
  • the invention is particularly suitable for devices with a pitch below 1 1 ⁇ m, since above this cell pitch the device may be stable even without using the invention.
  • the invention may be used for sizes significantly below 9 ⁇ m. If the 1 :2 active : inactive cell ratio of the embodiment does not provide a sufficient increase in linear stability for a particular cell size, then a different pattern, perhaps 1 :4 or 1 :6 ratio of active to inactive cells may be used. A 1 :4 or 1 :6 ratio is easy to obtain from a rectangular grid of cells.
  • n and p-type doped layers may be interchanged to obtain a p-type device.
  • the FET may be enhancement or depletion type, as required in any particular application.

Abstract

A vertical power MOSFET includes active cells 8 and inactive cells 10. The active cells 8 are surrounded by inactive cells 10 on the surface of the substrate, and are fewer in number. The MOSFET may have a lower zero temperature coefficient current than cells in which all cells are active.

Description

DESCRIPTION
INSULATED GATE FIELD EFFECT TRANSISTORS
The invention relates to insulated gate field effect transistors and methods of using them.
Power metal oxide semiconductor field effect transistors (MOSFETs) are generally used as switches in which they are either fully on or fully off. However, MOSFETs can also be used in a linear region of operation to self- protect the MOSFET from over-voltage spikes by turning on and absorbing power as part of a linear region of operation, typically using a dynamic current circuit, or to limit the current for a short period of time long enough for a decision to be made to switch the current to a safe state. Other circuits also require operation in the linear mode. For example, many simple motors are controlled in this way, such as fan motors.
A problem occurs when modern power MOSFETs, especially trench MOSFETs and vertical double diffused MOSFETS (VDMOS), are operated in the linear regime. Modern devices typically have small cell pitches (< 10μm) and these devices are susceptible to thermal runaway.
The reason for the thermal runaway in small devices is the existence of a critical current density Jc above which the current density decreases with increasing temperature but below which the current density increases with increasing temperature. If a FET is operated below the critical current density Jc a small increase in temperature increases current density, which causes an increase in temperature, causing still higher current density, i.e. thermal runaway.
The value of the critical current density Jc is determined by two competing effects. Firstly, as temperature increases the resistance of the channel increases. This decreases current density with increasing temperature. Secondly, as temperature increases, the threshold voltage of the MOSFET decreases. This change in threshold voltage does not matter when the MOSFET is switched hard on. However, in the linear regime, the decreased threshold voltage changes the effective gate voltage thereby increasing current density with increasing temperature. As the gain increases, the second effect becomes relatively more important. Modern MOSFETs have high values of gate width per unit area and are operated at currents such that the second effect is dominant, i.e. the MOSFETs are operated below Jc.
This means that modern power MOSFETs are susceptible to thermal runaway which can in turn lead to device failure.
As will be appreciated by the skilled person the problem is not limited to devices using oxide on silicon, but can occur in any power FET.
There is accordingly a need for a design of FET in which this problem is alleviated.
Some prior art relating to this problem exists. One solution is presented in US 5,095,043 which describes a complex arrangement with multiple source regions in each body region. Such a device is complex to manufacture.
Further devices are presented in US 6,664,594 which teaches a number of approaches. In one approach, cells are divided into two parts, the two parts having different threshold voltages. Again however this device is complex to manufacture. A further approach uses cells with different high and low threshold voltages, as set out in US2003/0230766. Again, however, the use of multiple different threshold voltages makes devices of this type difficult to manufacture.
According to the invention there is provided an insulated gate field effect transistor according to claim 1.
By providing a number of cells, some of which are active and some of which are completely inactive, the operation of the device in the linear regime is enhanced. The inventors have realised that it is not necessary to provide multiple different threshold voltages or cells that have asymmetric channels or complex forms. All that is required is that some of the cells are used and others are unused. The current may be uniformly spread over the device avoiding hot spots by virtue of the fact that the active cells are not crowded together. Preferably, the active cells are evenly distributed amongst the inactive cells.
A real benefit of the invention is that improved linear performance is obtained in an arrangement that is very easy to manufacture.
Preferably, the invention is implemented as a vertical transistor, wherein the gate is an insulated gate extending into the substrate from the first major surface.
In this arrangement it is easy to provide a power- MOS FET delivering the benefits of the invention.
The cells may include a body region of the FET, with an insulated gate in trenches between the cells. Source regions may be provided only in the active cells.
The cells may be arranged in a hexagonal array, and the ratio of active cells to inactive cells may be 1 :2. This is easy to arrange in a hexagonal array and provides enough active cells to pass current with the device turned on.
The cell pitch may be less than 1 1 μm. The invention is particularly applicable to devices with such small cell pitches, for which the zero temperature coefficient current may be particularly high and hence for which thermal instability is a particular problem.
The ratio of active cells to inactive cells may be 1 :2. This is a convenient ratio which gives good results for moderate cell pitches.
However, as the cell pitch is reduced a 1 :2 ratio of cells may result in a device that is unstable. In this case, it is possible to use a smaller number of active cells for each inactive cell. Accordingly, the invention includes devices wherein the cell pitch is 8 μm or less and the fraction of the number of active cells divided by the number of inactive cells has a value 1/3 or less.
In another aspect, there is provided a method according to claim 10.
The step of defining the transistor may include: etching a trench extending into the substrate from the first major surface between the cells; depositing gate insulator on the sidewalls and base of the trench; and filling the trench with gate conductor. The step of defining the transistor may further include: implanting a p-type body to form the cells; and after defining the trenches, implanting source regions adjacent to the trenches in the active cells but not the inactive cells.
Embodiments of the invention will now be described, purely by way of example, with reference to the accompanying drawings, in which:
Figure 1 shows a side view of an active cell and an inactive cell as used in the first embodiment of the invention;
Figure 2 shows a top view of a semiconductor device according to the first embodiment of the invention;
Figure 3 shows graphs of current against voltage at different temperatures for the first embodiment and a comparative example using only active cells;
Figure 4 shows pass and fail values of current and voltage for devices according to the invention and a comparative example; and
Figure 5 shows a top view of a semiconductor device of an alternative embodiment of the invention.
Referring to Figure 1 , a doped n+ semiconductor substrate 2 functions as the drain for a semiconductor device made up of a number of cells 6 at a first, top, major surface 4 of the substrate. The cells are divided into active cells 8 and inactive cells 10. The substrate may for example be a commercially available silicon substrate with a doping concentration in the range 1015 cm"3 to 1018 cm"3. Alternative materials and doping may be used if required.
A p-doped body region 12 is provided in each of the active cells 8 and the inactive cells 10. The cells 6 are separated by insulated gate trenches 14 which have a gate insulator 16 on the sidewalls and base of the trench and a conductor 18 within the trench to act as a gate. As may be seen in Figure 2, the cells 6 are distributed over the first major surface 4 of the substrate in a hexagonal array with the insulated gate trenches 14 connecting up so that the gate conductor 18 is linked.
The active cells 8 differ from the inactive cells 10 in that the active cells further comprise heavily doped n+ source regions 20 at the first major surface 4 in the body region 12, whereas these are omitted from the inactive cells 10.
An insulator 22 is arranged over the trenches 14 and partially over the source regions 20 to insulate the trench. The source region may for example be a ring shape leaving the centre of the ring as part of the body region 12. A metallisation layer 24 then extends over the surface of the insulator
22 and first major surface 4 making a source contact to the source regions 20 as well as the body regions 12. The trench has a similar width to depth in the range 1 μm to 3 μm. As will be appreciated, the trench depth and width can be varied depending on the device properties required. A back contact 28 is provided on the rear of the substrate 2 and a gate contact 30 is connected to the gate conductor 18.
Standard materials may be used for these contacts and metallisations 24, 28, 30, including for example Al and its alloys, such as AISi or polysilicon for the metallisation, and various contact materials as will be known to those skilled in the art and so will not be defined further. The gate insulator 16 may be made of any convenient material, including for example silicon oxide, silicon nitride and silicon oxynitride. Multiple layer gates may also be used if required.
The active cells 8 are distributed over the surface of the substrate as illustrated in Figure 2 in which the active cells 8 are shaded to distinguish them from the inactive cells 10. It will be seen that the pattern in this embodiment is a repeating pattern of two inactive cells 10 and one active cell 8, as indicated by the triangle 26, and so the ratio of inactive to active cells is 2:1.
The cell pitch, that is to say the distance between the centres of adjacent cells, in this embodiment is 9 μm. The device may be manufactured in a relatively conventional process which will accordingly not be described further. However, one modification is required so that the source diffusion is not carried out in the inactive cells. This is carried out by creating a mask pattern that covers the centre of the cell for the active cells, and covers the whole cell for the inactive cells, before carrying out an implantation step to implant the heavily doped n+ source regions 20 in the body region 12. In this way, the source regions 20 are created only in the active cells.
Experiments have been carried out on the device according to the embodiment and a comparative example using only active cells. The current- voltage characteristic is shown in Figure 3 at two temperatures. The leftmost two curves relate to the comparative example and the rightmost two curves to the embodiment. The two temperatures were 25 -C and 175 -C for each case. The zero temperature coefficient point is the current at which the same voltage is required to produce the current at different temperatures, i.e. the current at which the curves cross. As may be seen, the zero temperature coefficient point dropped from about 8OA in the comparative example to about 35A in the embodiment. Good yields of devices were obtained.
In the linear mode much better stability was obtained using the embodiment than using the comparative example. Figure 4 shows some failure points, i.e. values of current and voltage that when applied for a predetermined period caused failure. In some cases, a 100ms period was used, and in others a dc signal. 100ms failure points of the embodiment are labelled 32, at higher current values than the failure points of the comparative example 34. At dc, pass points of the embodiment, labelled 36, occur at very similar values to failure points 38 of the comparative example.
It may be seen that the embodiment produces much better results. Typical Rdson (resistance in the on state) values were 9 mOhm for the embodiment and 5.4mOhm for the comparative example. Since in the embodiment only one third of the cells are active this is a good result.
The invention is not restricted to the above embodiment. For example, the embodiment has cells that are the bodies of the transistors, surrounded by trenches. It is also possible to arrange the cells to be the trenches of the transistors, and the p-type bodies as the trench. In this case, the active cells may be provided by providing gate contacts only for the active cells and leaving the inactive cells with floating gates. The cells need not be hexagonal, but may be square, triangular, or any other suitable shape. Indeed, not all cells need to be the same. Such shapes and arrangements are taught in US 6,320,223 and the various cell variations taught therein are expressly included by reference.
In an alternative embodiment, illustrated in Figure 5, the first major surface may be divided into stripes 50, the active cells 8 being short regions of the stripes 50, the remainder of the stripes constituting an inactive cell 10. As may be seen in Figure 5, some stripes constitute only an inactive cell 10. Alternatively, all stripes may have active and inactive cells, for example by offsetting the active cells in adjacent stripes. Note that in these embodiments the cell size of the inactive cells 10 is greater than that of the active cells 8.
An alternative arrangement using stripes (not shown) has cells in the form of stripes arranged in parallel, the whole length of the stripe being either active or inactive. The active cell stripes (acting as a transistor) are interdispersed between inactive cell stripes.
Further, the cell pitch need not be the 9 μm of the embodiment. The invention is particularly suitable for devices with a pitch below 1 1 μm, since above this cell pitch the device may be stable even without using the invention.
The invention may be used for sizes significantly below 9 μm. If the 1 :2 active : inactive cell ratio of the embodiment does not provide a sufficient increase in linear stability for a particular cell size, then a different pattern, perhaps 1 :4 or 1 :6 ratio of active to inactive cells may be used. A 1 :4 or 1 :6 ratio is easy to obtain from a rectangular grid of cells.
Further, the n and p-type doped layers may be interchanged to obtain a p-type device.
The FET may be enhancement or depletion type, as required in any particular application.

Claims

1. A field effect transistor, comprising: a semiconductor substrate (2) having a first major surface (4); a plurality of cells (6) arranged across the substrate, the cells being divided into active cells (8) and inactive cells (10) each active cell (8) defining at least one operational transistor having an insulated gate (16,18), a source (22) and a drain (2); each inactive cell (10) not being operational as a transistor; wherein there are fewer active transistor cells than inactive cells (10).
2. A field effect transistor according to claim 1 wherein the inactive cells (10) surround the active cells (8) on the substrate (6).
3. A field effect transistor according to claim 1 or 2 in the form of a vertical transistor, wherein the gates of the cells (16,18) are insulated gates extending into the substrate in trenches (14) extending from the first major surface.
4. A field effect transistor according to claim 3 wherein the cells (8) include a body region (12) of the FET, the insulated gate (18) is provided in the trenches (14) between the cells, and source regions (20) adjacent to the trenches (18) are provided only in the active cells (8).
5. A field effect transistor according to any preceding claim wherein the cells are arranged in a hexagonal array.
6. A field effect transistor according to any of claims 1 to 4 comprising a plurality of stripes (50) extending across the substrate, the active cells (8) being defined as lengths of at least some of the stripes (50), the remainder of the stripes defining inactive cells (10).
7. A field effect transistor according to any preceding claim wherein the cell pitch is less than 1 1 μm.
8. A field effect transistor according to any preceding claim wherein the ratio of active cells (8) to inactive cells (10) is 1 :2.
9. A field effect transistor according to any of claims 1 to 5 wherein the cell pitch is 8 μm or less and the fraction of the number of active cells (8) divided by the number of inactive cells (10) has a value 1/3 or less.
10. A method of manufacturing a field effect transistor, comprising providing a semiconductor substrate (2) having a first major surface (4); and defining a plurality of cells (6) arranged across the substrate, the cells being divided into active cells (8) and inactive cells (10), each active cell (8) defining at least one operational transistor having an insulated gate (16,18), a source (22) and a drain (2) each inactive cell (10) not being operational as a transistor; wherein there are fewer active transistor cells than inactive cells (10).
1 1. A method according to claim 10 wherein the inactive cells (10) surround the active cells (8) on the substrate (6).
12. A method according to claim 10 or 1 1 wherein the step of defining the transistor includes: etching a trench (14) extending into the substrate from the first major surface between the cells; depositing gate insulator (16) on the sidewalls and base of the trench (14); and filling the trench (14) with gate conductor (18).
13. A field effect transistor according to claim 12 wherein the step of defining the transistor further includes: implanting a p-type body to form the cells (8); and after defining the trenches, implanting source regions (20) adjacent to the trenches (14) in the active cells (8) but not the inactive cells (10).
14. A method according to any of claims 1 1 , 12 or 13 wherein the cells (6) are arranged in a hexagonal array.
PCT/IB2005/053994 2004-12-02 2005-12-01 Insulated gate field effect transistors WO2006059300A2 (en)

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US10651276B2 (en) 2018-03-15 2020-05-12 Kabushiki Kaisha Toshiba Semiconductor device
US11728422B2 (en) 2019-11-14 2023-08-15 Stmicroelectronics S.R.L. Power MOSFET device having improved safe-operating area and on resistance, manufacturing process thereof and operating method thereof
US11798981B2 (en) 2020-06-23 2023-10-24 Stmicroelectronics S.R.L. 4H—SiC electronic device with improved short-circuit performances, and manufacturing method thereof

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CN105895684B (en) * 2015-10-16 2018-12-28 苏州能讯高能半导体有限公司 A kind of semiconductor devices and its manufacturing method

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EP0022001A1 (en) * 1979-06-29 1981-01-07 Thomson-Csf High-frequency vertical field effect power transistor and method of making such a transistor
EP0889531A1 (en) * 1997-06-30 1999-01-07 Asea Brown Boveri AG MOS-controlled semiconductor device
DE19808348C1 (en) * 1998-02-27 1999-06-24 Siemens Ag Semiconductor component, such as field-effect power semiconductor device

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EP0889531A1 (en) * 1997-06-30 1999-01-07 Asea Brown Boveri AG MOS-controlled semiconductor device
DE19808348C1 (en) * 1998-02-27 1999-06-24 Siemens Ag Semiconductor component, such as field-effect power semiconductor device

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Publication number Priority date Publication date Assignee Title
US10651276B2 (en) 2018-03-15 2020-05-12 Kabushiki Kaisha Toshiba Semiconductor device
US11728422B2 (en) 2019-11-14 2023-08-15 Stmicroelectronics S.R.L. Power MOSFET device having improved safe-operating area and on resistance, manufacturing process thereof and operating method thereof
US11798981B2 (en) 2020-06-23 2023-10-24 Stmicroelectronics S.R.L. 4H—SiC electronic device with improved short-circuit performances, and manufacturing method thereof

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GB0426412D0 (en) 2005-01-05
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JP2008523586A (en) 2008-07-03
CN101288178A (en) 2008-10-15

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