JP2008311614A - プリント基板のペーストバンプ形成方法 - Google Patents
プリント基板のペーストバンプ形成方法 Download PDFInfo
- Publication number
- JP2008311614A JP2008311614A JP2007337555A JP2007337555A JP2008311614A JP 2008311614 A JP2008311614 A JP 2008311614A JP 2007337555 A JP2007337555 A JP 2007337555A JP 2007337555 A JP2007337555 A JP 2007337555A JP 2008311614 A JP2008311614 A JP 2008311614A
- Authority
- JP
- Japan
- Prior art keywords
- paste
- bump
- printed circuit
- circuit board
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
- H05K2203/0139—Blade or squeegee, e.g. for screen printing or filling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49204—Contact or terminal manufacturing
- Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
- Y10T29/49222—Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
- Y10T29/532—Conductor
- Y10T29/53243—Multiple, independent conductors
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
【解決手段】本発明のプリント基板のペーストバンプ形成方法は、原板を準備する段階と、原板に導電性ペーストを印刷した後に(S10)乾燥させて(S20)第1ペーストバンプ20aを形成する段階と、コイニング工程を実施して(S30)第1ペーストバンプ20aの上面を平らにする段階と、第1ペーストバンプ20a上に導電性ペーストを印刷した後に(S40)乾燥させて(S50)第2ペーストバンプ20bを形成する段階とを含むことを特徴とする。
【選択図】図3
Description
次に、原板100上に印刷された導電性ペーストを乾燥させる(S200)。
20、200 ペーストバンプ
Claims (10)
- a)原板を準備する段階と、
b)前記原板に導電性ペーストを印刷した後、乾燥させて第1ペーストバンプを形成する段階と、
c)コイニング工程を実施して前記第1ペーストバンプの上面を平らにする段階と、
d)前記第1ペーストバンプ上に導電性ペーストを印刷した後、乾燥させて第2ペーストバンプを形成する段階と
を含むことを特徴とするプリント基板のペーストバンプ形成方法。 - 前記b)段階は、
b−1)第1の大きさのホールが形成された第1マスクを、前記原板上にのせる段階と、
b−2)前記第1マスク上に導電性ペーストを塗布した後、スキージで前記導電性ペーストを印刷する段階と、
b−3)前記第1の大きさのホールに前記導電性ペーストを充填して前記導電性ペーストの下端を前記原板に圧着する段階と、
b−4)前記第1マスクを除去した後、前記導電性ペーストを乾燥させて前記第1ペーストバンプを形成する段階と
を含むことを特徴とする請求項1に記載のプリント基板のペーストバンプ形成方法。 - 前記d)段階は、
d−1)第2の大きさのホールが形成された第2マスクを、前記第1ペーストバンプ上にのせる段階と、
d−2)前記第2マスク上に導電性ペーストを塗布した後、スキージで前記導電性ペーストを印刷する段階と、
d−3)前記第2の大きさのホールに前記導電性ペーストを充填して前記導電性ペーストの下端を前記第1ペーストバンプの上面に圧着する段階と、
d−4)前記第2マスクを除去した後、前記導電性ペーストを乾燥させて前記第2ペーストバンプを形成する段階と
を含むことを特徴とする請求項1または請求項2に記載のプリント基板のペーストバンプ形成方法。 - 前記第2マスクに形成されたホールの大きさは、前記第1マスクに形成されたホールの大きさと同一またはより小さく形成されていることを特徴とする請求項3に記載のプリント基板のペーストバンプ形成方法。
- 前記第2マスクは、前記第1マスクと同一またはより低い高さを持つことを特徴とする請求項3または請求項4に記載のプリント基板のペーストバンプ形成方法。
- 前記原板は、絶縁層の片面に回路パターンが形成されていることを特徴とする請求項1乃至請求項5のいずれか1項に記載のプリント基板のペーストバンプ形成方法。
- 前記原板は、絶縁層の両面に回路パターンが形成されていることを特徴とする請求項1乃至請求項5のいずれか1項に記載のプリント基板のペーストバンプ形成方法。
- 前記原板は、金属キャリアの片面に銅箔が積層されていることを特徴とする請求項1乃至請求項5のいずれか1項に記載のプリント基板のペーストバンプ形成方法。
- 前記原板は、銅箔であることを特徴とする請求項1乃至請求項5のいずれか1項に記載のプリント基板のペーストバンプ形成方法。
- 前記第2ペーストバンプは、前記第1ペーストバンプと同一の高さまたはより低い高さを持つことを特徴とする請求項1乃至請求項9のいずれか1項に記載のプリント基板のペーストバンプ形成方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070057370A KR100871034B1 (ko) | 2007-06-12 | 2007-06-12 | 인쇄회로기판의 페이스트 범프 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008311614A true JP2008311614A (ja) | 2008-12-25 |
JP4637893B2 JP4637893B2 (ja) | 2011-02-23 |
Family
ID=40131008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007337555A Expired - Fee Related JP4637893B2 (ja) | 2007-06-12 | 2007-12-27 | プリント基板のペーストバンプ形成方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7841074B2 (ja) |
JP (1) | JP4637893B2 (ja) |
KR (1) | KR100871034B1 (ja) |
CN (1) | CN101325843B (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101214730B1 (ko) * | 2010-03-22 | 2012-12-21 | 삼성전기주식회사 | 세라믹 그린시트 제조장치 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07336019A (ja) * | 1994-06-10 | 1995-12-22 | Sumitomo Metal Ind Ltd | 導体パターンの形成方法 |
JPH08316601A (ja) * | 1995-05-15 | 1996-11-29 | Tokuyama Corp | 回路基板及びその製造方法 |
JPH0955451A (ja) * | 1995-08-11 | 1997-02-25 | Samsung Aerospace Ind Ltd | 導電性インクを使用した半導体パッケージ基板の製造方法 |
JPH10116927A (ja) * | 1996-10-09 | 1998-05-06 | Sumitomo Metal Ind Ltd | 接続端子及びその形成方法 |
JP2000133145A (ja) * | 1998-10-30 | 2000-05-12 | Mitsubishi Electric Corp | 面放電型プラズマディスプレイパネル用基板及びその製造方法、面放電型プラズマディスプレイパネル及びその製造方法、並びに面放電型プラズマディスプレイ装置 |
JP2001257230A (ja) * | 2000-03-13 | 2001-09-21 | Denso Corp | 電子部品の実装方法 |
JP2002217531A (ja) * | 2001-01-12 | 2002-08-02 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
JP2003309369A (ja) * | 2002-04-16 | 2003-10-31 | Seiko Epson Corp | 多層配線基板、多層配線基板の製造方法、電子デバイス及び電子機器 |
JP2005286166A (ja) * | 2004-03-30 | 2005-10-13 | Nec Electronics Corp | コイニング装置およびコイニング方法 |
JP2005353726A (ja) * | 2004-06-09 | 2005-12-22 | Shinko Electric Ind Co Ltd | 半導体パッケージの製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2794731B2 (ja) * | 1988-11-30 | 1998-09-10 | 富士通株式会社 | はんだバンプの形成方法 |
JP2788694B2 (ja) * | 1992-09-25 | 1998-08-20 | ローム株式会社 | 電子部品におけるバンプ電極の形成方法 |
JP3385872B2 (ja) * | 1995-12-25 | 2003-03-10 | 三菱電機株式会社 | はんだ供給法およびはんだ供給装置 |
JP3423239B2 (ja) | 1998-01-22 | 2003-07-07 | リコーマイクロエレクトロニクス株式会社 | バンプ電極形成方法 |
JP3831179B2 (ja) * | 1999-06-29 | 2006-10-11 | 株式会社東芝 | 半導体装置の製造方法およびパターン形成方法 |
US6889433B1 (en) * | 1999-07-12 | 2005-05-10 | Ibiden Co., Ltd. | Method of manufacturing printed-circuit board |
JP3403677B2 (ja) * | 1999-09-06 | 2003-05-06 | マイクロ・テック株式会社 | 半田ボール形成方法 |
JP2001230537A (ja) * | 2000-02-17 | 2001-08-24 | Ngk Spark Plug Co Ltd | ハンダバンプの形成方法 |
JP2003298215A (ja) * | 2002-04-01 | 2003-10-17 | Cmk Corp | プリント配線板の製造方法 |
KR100704922B1 (ko) * | 2005-11-16 | 2007-04-09 | 삼성전기주식회사 | 페이스트 범프를 이용한 인쇄회로기판 및 그 제조방법 |
US7422973B2 (en) * | 2006-01-27 | 2008-09-09 | Freescale Semiconductor, Inc. | Method for forming multi-layer bumps on a substrate |
KR100657406B1 (ko) * | 2006-02-15 | 2006-12-14 | 삼성전기주식회사 | 다층 인쇄회로기판 제조방법 |
-
2007
- 2007-06-12 KR KR1020070057370A patent/KR100871034B1/ko not_active IP Right Cessation
- 2007-12-27 JP JP2007337555A patent/JP4637893B2/ja not_active Expired - Fee Related
- 2007-12-27 US US12/005,353 patent/US7841074B2/en not_active Expired - Fee Related
- 2007-12-28 CN CN2007103060856A patent/CN101325843B/zh not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07336019A (ja) * | 1994-06-10 | 1995-12-22 | Sumitomo Metal Ind Ltd | 導体パターンの形成方法 |
JPH08316601A (ja) * | 1995-05-15 | 1996-11-29 | Tokuyama Corp | 回路基板及びその製造方法 |
JPH0955451A (ja) * | 1995-08-11 | 1997-02-25 | Samsung Aerospace Ind Ltd | 導電性インクを使用した半導体パッケージ基板の製造方法 |
JPH10116927A (ja) * | 1996-10-09 | 1998-05-06 | Sumitomo Metal Ind Ltd | 接続端子及びその形成方法 |
JP2000133145A (ja) * | 1998-10-30 | 2000-05-12 | Mitsubishi Electric Corp | 面放電型プラズマディスプレイパネル用基板及びその製造方法、面放電型プラズマディスプレイパネル及びその製造方法、並びに面放電型プラズマディスプレイ装置 |
JP2001257230A (ja) * | 2000-03-13 | 2001-09-21 | Denso Corp | 電子部品の実装方法 |
JP2002217531A (ja) * | 2001-01-12 | 2002-08-02 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
JP2003309369A (ja) * | 2002-04-16 | 2003-10-31 | Seiko Epson Corp | 多層配線基板、多層配線基板の製造方法、電子デバイス及び電子機器 |
JP2005286166A (ja) * | 2004-03-30 | 2005-10-13 | Nec Electronics Corp | コイニング装置およびコイニング方法 |
JP2005353726A (ja) * | 2004-06-09 | 2005-12-22 | Shinko Electric Ind Co Ltd | 半導体パッケージの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN101325843A (zh) | 2008-12-17 |
JP4637893B2 (ja) | 2011-02-23 |
US7841074B2 (en) | 2010-11-30 |
KR100871034B1 (ko) | 2008-11-27 |
US20080307641A1 (en) | 2008-12-18 |
CN101325843B (zh) | 2010-06-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5022392B2 (ja) | ペーストバンプを用いた印刷回路基板の製造方法 | |
WO2018110437A1 (ja) | 配線基板、多層配線基板、及び配線基板の製造方法 | |
KR100832650B1 (ko) | 다층 인쇄회로기판 및 그 제조 방법 | |
JP2013106034A (ja) | プリント回路基板の製造方法 | |
KR100782404B1 (ko) | 인쇄회로기판 및 그 제조방법 | |
JP2007005815A (ja) | 多層印刷回路基板およびその製造方法 | |
KR100752017B1 (ko) | 인쇄회로기판의 제조방법 | |
JP2014022715A (ja) | コアレス基板及びその製造方法 | |
JP2009021545A (ja) | 印刷回路基板の製造方法 | |
CN104703399A (zh) | 电路板及其制作方法 | |
JP4637893B2 (ja) | プリント基板のペーストバンプ形成方法 | |
TWI376171B (en) | A printed circuit board having an embedded electronic component and a method thereof | |
JP4553950B2 (ja) | 印刷回路基板及びその製造方法 | |
JP2005045163A (ja) | 多層回路板の製造方法 | |
KR100796981B1 (ko) | 인쇄회로기판 제조방법 | |
KR100658972B1 (ko) | 인쇄회로기판 및 그 제조방법 | |
JP2008124124A (ja) | コア基板の製造方法及び配線基板の製造方法 | |
KR100771283B1 (ko) | 인쇄회로기판의 비아홀 충진 방법 | |
JP2012134502A (ja) | 多層印刷回路基板及びその製造方法 | |
KR101081153B1 (ko) | 임베디드 미세회로 기판 제조 방법 | |
JP2013122961A (ja) | 配線基板、配線基板の製造方法 | |
KR100704917B1 (ko) | 인쇄회로기판 및 그 제조방법 | |
KR100871031B1 (ko) | 인쇄회로기판의 범프 형성방법 | |
KR20110030160A (ko) | 인쇄회로기판의 제조방법 | |
JP2006093303A (ja) | プリント配線板およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100420 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101116 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20101124 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131203 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |