JP2008311520A - 電子部品内蔵基板の製造方法 - Google Patents
電子部品内蔵基板の製造方法 Download PDFInfo
- Publication number
- JP2008311520A JP2008311520A JP2007159223A JP2007159223A JP2008311520A JP 2008311520 A JP2008311520 A JP 2008311520A JP 2007159223 A JP2007159223 A JP 2007159223A JP 2007159223 A JP2007159223 A JP 2007159223A JP 2008311520 A JP2008311520 A JP 2008311520A
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- Prior art keywords
- substrate
- electronic component
- semiconductor chip
- resin
- hole
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- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
- Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
- Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
- Y10T29/49172—Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Combinations Of Printed Boards (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】半導体チップ110を第1の基板100に搭載する工程と、半導体チップ110と第1の基板100との間にアンダーフィル樹脂109を配設する工程と、第2の基板200に貫通孔206を形成する工程と、第2の基板200に電極112を設ける工程と、電極112により内部に半導体チップ110が内蔵されるよう第1及び第2の基板100,200を接合する工程と、貫通孔206からエアー抜きを行いつつ、半導体チップ110及び第1の基板100に発生した反りを是正できる充填圧力で第1及び第2の基板100.200間に封止樹脂115を充填する工程とを有する。
【選択図】図8
Description
第1の基板に形成された該配線と接続されるよう電子部品を前記第1の基板に搭載する第1の工程と、
前記電子部品と前記第1の基板との間にアンダーフィル樹脂を配設する第2の工程と、
配線が形成された前記第2の基板の前記電子部品と対向する領域内に単数又は複数の孔を形成する第3の工程と、
前記第2の基板に少なくとも金属コアを含む電極を設ける第4の工程と、
前記電極を前記第1の基板の配線に接合することにより、前記電子部品が内蔵されるよう前記第1の基板と前記第2の基板を接合する第5の工程と、
前記第2の基板に形成された孔からエアー抜きを行いつつ、かつ、前記電子部品及び前記第1の基板に発生した反りを是正しうる充填圧力が前記電子部品及び前記第1の基板に印加されるよう、前記第1の基板と前記第2の基板との間に樹脂を充填する第6の工程とを有する電子部品内蔵基板の製造方法により解決することができる。
前記第2の基板と金型との間に前記孔を覆うようフィルムを配設しつつ、接合された前記第1及び第2の基板を金型に装着し、前記第1の基板と前記第2の基板との離間部分に樹脂を充填することとしてもよい。
101 コア基板
103A,103B,203A,203B 配線パターン
104A,104B,204A,204B ソルダーレジスト層
109 アンダーフィル
110 半導体チップ
111 はんだボール
112 電極
113 銅コア
114 はんだ被膜
115 封止樹脂
200 第2の基板
201 コア基板
206 貫通孔
300 金型
305 離型フィルム
308 気泡
400 電子部品内蔵基板
Claims (6)
- 第1の基板に形成された配線と接続されるよう電子部品を前記第1の基板に搭載する第1の工程と、
前記電子部品と前記第1の基板との間にアンダーフィル樹脂を配設する第2の工程と、
配線が形成された第2の基板の前記電子部品と対向する領域内に単数又は複数の孔を形成する第3の工程と、
前記第2の基板に少なくとも金属コアを含む電極を設ける第4の工程と、
前記電極を前記第1の基板の配線に接合することにより、前記電子部品が内蔵されるよう前記第1の基板と前記第2の基板を接合する第5の工程と、
前記第2の基板に形成された孔からエアー抜きを行いつつ、かつ、前記電子部品及び前記第1の基板に発生した反りを是正しうる充填圧力が前記電子部品及び前記第1の基板に印加されるよう、前記第1の基板と前記第2の基板との間に樹脂を充填する第6の工程と
を有する電子部品内蔵基板の製造方法。 - 前記第6の工程では、
前記第2の基板と金型との間に前記孔を覆うようフィルムを配設しつつ、接合された前記第1及び第2の基板を金型に装着し、前記第1の基板と前記第2の基板との離間部分に樹脂を充填する請求項1記載の電子部品内蔵基板の製造方法。 - 前記孔を、前記第2の基板の前記電子部品と対向する領域の中央位置に形成した請求項1又は2記載の電子部品内蔵基板の製造方法。
- 複数の前記孔を、前記第2の基板の前記電子部品と対向する領域の中央位置を含み、前記樹脂の充填方向に沿って直線状に列設した請求項1又は2記載の電子部品内蔵基板の製造方法。
- 前記電極は、少なくとも金属コアを含む請求項1乃至4のいずれか一項に記載の電子部品内蔵基板の製造方法。
- 前記第6の工程では、
前記第2の基板に形成された孔からエアー抜きを行いつつ、かつ、前記電子部品及び前記第1の基板に発生した反りを是正しうる充填圧力が前記電子部品及び前記第1の基板に印加されるよう樹脂を充填する請求項1乃至5のいずれか一項に記載の電子部品内蔵基板の製造方法。
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JP2011159799A (ja) * | 2010-02-01 | 2011-08-18 | Dainippon Printing Co Ltd | パッケージ化半導体装置、パッケージ化半導体装置の製造方法 |
KR20150116605A (ko) * | 2014-04-08 | 2015-10-16 | 삼성전기주식회사 | 전자 소자 모듈 및 그 제조 방법 |
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JP6044473B2 (ja) * | 2013-06-28 | 2016-12-14 | 株式会社デンソー | 電子装置およびその電子装置の製造方法 |
KR20150025129A (ko) * | 2013-08-28 | 2015-03-10 | 삼성전기주식회사 | 전자 소자 모듈 및 그 제조 방법 |
US10356911B2 (en) * | 2014-07-04 | 2019-07-16 | Samsung Electro-Mechanics Co., Ltd. | Electronic device module and method of manufacturing the same |
US9859200B2 (en) * | 2014-12-29 | 2018-01-02 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof |
JP6566879B2 (ja) * | 2016-01-28 | 2019-08-28 | 新光電気工業株式会社 | 電子部品内蔵基板 |
JP7257978B2 (ja) * | 2020-01-20 | 2023-04-14 | 三菱電機株式会社 | 半導体装置 |
CN111328215B (zh) * | 2020-02-21 | 2021-06-18 | 竞华电子(深圳)有限公司 | 印制电路板制造方法及印制电路板 |
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