JP2008277757A - 半導体チップと基板との間の半田接続部およびその製造 - Google Patents
半導体チップと基板との間の半田接続部およびその製造 Download PDFInfo
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- JP2008277757A JP2008277757A JP2008050828A JP2008050828A JP2008277757A JP 2008277757 A JP2008277757 A JP 2008277757A JP 2008050828 A JP2008050828 A JP 2008050828A JP 2008050828 A JP2008050828 A JP 2008050828A JP 2008277757 A JP2008277757 A JP 2008277757A
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Abstract
【解決手段】基板3は、半田付け可能な表面領域4を有しており、当該半田付け可能な表面領域4上には、半田層が配置される。当該半田層には、上記半導体チップの裏面10が固定される。上記半田層は、繰り返し溶解可能かつ耐真空性の半田材料6を含んでいる。上記半田接続部1を製造するためには、まずボンディングプロセスによって、上記表面領域上に上記半導体チップ2が固定される。次に、空隙を含まない半田層を達成するために、溶融状態にある上記半田層を有する、ボンディングされた半田接続部1が、真空半田付け炉内において真空引きされる。
【選択図】図1
Description
本発明は、半導体チップと基板との間の半田接続部(soldered connection)、およびその製造プロセスに関する。このような基板は通常、半田付け可能な表面領域を有しており、当該表面領域上に半田材料層が形成される。当該半田材料層上には、半導体チップの裏面が固定される。この固定は、ダイボンディングプロセスによって行われる。しかしダイボンディング技術は、チップ面積が25mm2を超える場合、および電力損失密度(power loss density)が大きい場合には適さない。これは、ダイボンディング中に半田層内に形成される空隙によって電流分布が不均一となり、これによって局所的な過熱が生じるため、半導体デバイスの動作中に基板から半導体チップが分離する現象が起こるためである。さらに、ダイボンディング後の製造工程において温度が上昇した場合、空隙内に捕獲されていた揮発性物質によって応力が掛けられ、半田材料層が損傷する危険性がある。
半導体チップと、半田材料層が上部に形成される、半田付け可能な表面領域を有する基板との間に位置する、半田接続部が示されている。当該半導体チップの裏面は、当該半田材料層に固定されており、当該半田材料層は、繰り返し溶解可能かつ耐真空性の半田材料を含んでいる。
本発明の典型的な実施形態について、添付図面を参照しながら以下に説明する。これらの図面では、同様の参照符号は同様の箇所を示している。図面は以下の通りである:
図1は、典型的な半田接続部の概略断面図である。
図1は、典型的な半田接続部1の概略的な断面である。半田接続部1は、半導体チップ2と、半田付け可能な表面領域4を有する基板3との間に形成される。半田付け可能な表面領域4上には、半田材料層5が形成される。半田材料層5は、繰り返し溶解可能かつ耐真空性である、半田材料6を含有している。典型的な本実施形態では、半田材料6は、SnAg、PbSnAg、PbSn、あるいはPbSnInから成る群から選択された材料を含有しており、基板3は、リードフレーム8のチップアイランド7によって形成された表面領域4を有している。リードフレーム8は、チップアイランド7に加えて、リード26をさらに有している。当該リード26は、例えば、チップアイランド7を囲み、また半導体デバイスの外部端子を形成する外部リード内に伸びている。
Claims (43)
- 半導体チップと基板との間の半田接続部であって、
半田付け可能な表面領域を有する基板と、
少なくとも1つの半導体チップと、
上記半導体チップと上記基板の上記表面領域との間に位置しており、且つ、繰り返し溶解可能且つ耐真空性の半田材料を含有した半田材料層とを含んでいる、半田接続部。 - 上記半田材料層は、SnAg、PbSnAg、PbsN、あるいはPbSnInからなる群のいずれか1つの半田材料を含有している、請求項1に記載の半田接続部。
- 上記表面領域および上記半導体チップの面積Aは、25mm2以上である、請求項1または請求項2に記載の半田接続部。
- 上記表面領域および上記半導体チップの面積Aは、225mm2以上である、請求項1〜請求項3のいずれか一項に記載の半田接続部。
- 上記半導体チップはパワー半導体チップである、請求項1〜請求項4のいずれか一項に記載の半田接続部。
- 上記表面領域は、銅、銀、ニッケル、ニッケル/パラジウム/金、あるいはこれらの合金からなる群のいずれか1つの材料を含有している、請求項1〜請求項5のいずれか一項に記載の半田接続部。
- 上記基板は、表面領域としてリードフレームのチップアイランドを含んでいる、請求項1〜請求項6のいずれか一項に記載の半田接続部。
- 上記基板は絶縁材料を含んでおり、上記表面領域は金属積層または金属被膜を含んでいる、請求項1〜請求項7のいずれか一項に記載の半田接続部。
- 上記絶縁材料はセラミックを含有している、請求項8に記載の半田接続部。
- 上記絶縁材料はプラスチックを含有している、請求項8に記載の半田接続部。
- 上記半導体チップは、裏面が上記表面領域内の上記半田材料層上に配置されており、且つ、当該裏面上において、アルミニウム、金、銀、あるいはパラジウム/金、あるいはこれらの合金のうちのいずれか1つの材料から成る被膜を含んでいる、請求項1〜請求項10のいずれか一項に記載の半田接続部。
- 上記基板は、シリコン結晶から成る半導体チップよりも高い熱伝導率を有している、請求項1〜請求項11のいずれか一項に記載の半田接続部。
- 上記表面領域は、上記半導体チップよりも広い二次元的範囲を有している、請求項1〜請求項12のいずれか一項に記載の半田接続部。
- 上記基板上には、多数の半導体チップが互いに隣接して配置されている、請求項1〜請求項13のいずれか一項に記載の半田接続部。
- 上記基板は、パターン形成された金属被膜を上面に有している、請求項14に記載の半田接続部。
- 上記パターン形成された金属被膜は、少なくとも1つのチップアイランドと、素子を上記半導体チップの接触領域に接続する接触端子領域とを含んでいる、請求項1〜請求項15のいずれか一項に記載の半田接続部。
- 半田接続部を製造するプロセスであって、
半田付け可能な表面領域を有する基板を設ける工程と、
上面および半田付け可能な裏面を有する半導体チップを設ける工程と、
上記半田付け可能な表面領域あるいは上記半田付け可能な裏面に、半田材料を塗布する工程と、
上記半導体チップを、第1の溶解によって上記基板に一体的にボンディングし、そして上記表面領域と上記裏面との間に半田材料層を形成するために上記半田材料を配置する工程と、
上記一体的にボンディングされた構造を、真空引き可能な加熱スペース内に導入する工程と、
上記半田材料に対して真空下において第2の溶解を行うことによって、上記半田材料層から揮発性物質を排出させ、次に、半田接続部を形成するために上記半田材料を配置する工程とを含んでいる、プロセス。 - 上記第1の溶解および第2の溶解は、上記半田材料の融点と同じ融点で行われる(TS1=TS2)、請求項17に記載のプロセス。
- 上記第1の溶解のための上記融点(TS1)は、上記第2の溶解のための上記融点(TS2)よりも低い、請求項17に記載のプロセス。
- 上記半導体チップを上記基板に一体的にボンディングする上記工程のために、ダイボンディングプロセスが用いられる、請求項17〜請求項19のいずれか一項に記載のプロセス。
- 上記半導体チップを上記基板に一体的にボンディングする上記工程のために、標準化されたダイボンダ(standardized die bonder)が用いられる、請求項20に記載のプロセス。
- 真空下において上記半田材料に対して上記第2の溶解を行う上記工程のために、標準化された真空半田付け炉が用いられる、請求項17〜請求項21のいずれか一項に記載のプロセス。
- 上記ダイボンディングおよび真空溶解のために、基板の多数の半田付け可能な表面領域上に多数の半導体チップが配置されるバッチ処理が用いられる、請求項17〜請求項22のいずれか一項に記載のプロセス。
- 上記ダイボンディングおよび真空溶解のために、少なくとも1つのダイボンディング位置および真空炉位置を含む連続枚葉式製造装置(continuous production installation)内において多数の半導体チップが次々と処理される連続的なプロセスが用いられる、請求項17〜請求項22のいずれか一項に記載のプロセス。
- 上記半田付け可能な表面領域あるいは上記半田付け可能な裏面に半田材料を塗布するために、低フラックス(low-flux)の半田材料が塗布される、請求項17〜請求項24のいずれか一項に記載のプロセス。
- 上記半田付け可能な表面領域あるいは上記半田付け可能な裏面に、半田材料として、SnAg、PbSnAg、PbsN、あるいはPbSnInからなる群のうちのいずれか1つの材料が塗布される、請求項17〜請求項24のいずれか一項に記載のプロセス。
- 25mm2以上の面積Aを有する上記表面領域と上記半導体チップとの間に、半田接続部が製造される、請求項17〜請求項26のいずれか一項に記載のプロセス。
- 225mm2以上の面積Aを有する上記表面領域と上記半導体チップとの間に、半田接続部が製造される、請求項17〜請求項26のいずれか一項に記載のプロセス。
- 上記表面領域とパワー半導体チップとの間に、半田接続部が製造される、請求項17〜請求項28のいずれか一項に記載のプロセス。
- 上記半田接続部の上記基板の上記表面領域として、リードフレームのチップアイランドが用いられる、請求項17〜請求項29のいずれか一項に記載のプロセス。
- 上記表面領域に半田材料を塗布する上記工程の前に、上記表面領域が、銅、銀、ニッケル、ニッケル/パラジウム/金、あるいはこれらの合金からなる群のうちのいずれか1つの材料によって被覆される、請求項17〜請求項29のいずれか一項に記載のプロセス。
- 上記基板としてセラミックシートが用いられる、請求項17〜請求項31のいずれか一項に記載のプロセス。
- 上記基板としてプラスチックシートが用いられる、請求項17〜請求項31のいずれか一項に記載のプロセス。
- 上記半田接続部を製造する上記工程の前に、上記半導体チップの上記裏面が、アルミニウム、金、銀、あるいはパラジウム/金、あるいはこれらの合金からなる群のうちのいずれか1つの材料によって被覆される、請求項17〜請求項33のいずれか一項に記載のプロセス。
- 上記半導体チップはシリコン結晶ウェハから製造される、請求項17〜請求項34のいずれか一項に記載のプロセス。
- 半田接続部を製造する上記工程の前に、少なくとも1つのチップアイランドと、上記半導体チップの接触領域に部材を接続するための接触端子領域とを有する、パターン形成された金属被膜が上記基板に形成される、請求項17〜請求項35のいずれか一項に記載のプロセス。
- 上記基板の全表面積が金属で被覆され、次に、パターン形成された金属被膜を形成する上記工程のために、パターン形成されたレジストマスクがフォトリソグラフィによって形成される、請求項36に記載のプロセス。
- パターン形成された金属被膜を形成する上記工程のために、ドライエッチング処理またはウェットエッチング処理が行われ、当該ドライエッチング処理中または当該ウェットエッチング処理中に、上記レジストマスクが上記パターン形成された金属被膜が形成されるように保護し、当該保護後に上記レジストマスクが除去される、請求項36または請求項37に記載のプロセス。
- 上記全面積金属被膜は、レーザービームによってパターン形成される、請求項37に記載のプロセス。
- 上記パターン形成された金属被膜は、印刷法によって形成される、請求項36に記載のプロセス。
- 上記パターン形成された金属被膜は、スクリーン印刷法によって形成される、請求項36に記載のプロセス。
- 上記パターン形成された金属被膜は、ステンシル印刷法によって形成される、請求項36に記載のプロセス。
- 上記パターン形成された金属被膜は、ジェット印刷法によって形成される、請求項36に記載のプロセス。
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JP2011061170A (ja) * | 2009-09-04 | 2011-03-24 | Paragon Semiconductor Lighting Technology Co Ltd | 放熱効果を高め発光効率を向上させることができる発光ダイオードのパッケージ構造とその製作方法 |
CN101920405A (zh) * | 2010-08-23 | 2010-12-22 | 中国电力科学研究院 | 一种镀锌钢接地网用锡铅基复合钎料及其制备方法 |
CN101920405B (zh) * | 2010-08-23 | 2013-07-31 | 中国电力科学研究院 | 一种镀锌钢接地网用锡铅基复合钎料及其制备方法 |
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DE102007010882B4 (de) | 2009-01-29 |
DE102007010882A1 (de) | 2008-09-25 |
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