JP2008277750A - 電子素子内蔵印刷回路基板の製造方法 - Google Patents

電子素子内蔵印刷回路基板の製造方法 Download PDF

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JP2008277750A
JP2008277750A JP2008028551A JP2008028551A JP2008277750A JP 2008277750 A JP2008277750 A JP 2008277750A JP 2008028551 A JP2008028551 A JP 2008028551A JP 2008028551 A JP2008028551 A JP 2008028551A JP 2008277750 A JP2008277750 A JP 2008277750A
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Prior art keywords
circuit board
printed circuit
manufacturing
built
connection
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Japanese (ja)
Inventor
Jee-Soo Mok
智 秀 睦
Jun Hyung Park
俊 炯 朴
Ki-Hwan Kim
起 換 金
Sung-Yong Kim
成 容 金
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014091624A1 (ja) * 2012-12-14 2014-06-19 株式会社メイコー 部品内蔵基板および部品内蔵基板の製造方法
JP2015060912A (ja) * 2013-09-18 2015-03-30 日立化成株式会社 半導体素子搭載用パッケージ基板
KR20150102504A (ko) * 2014-02-28 2015-09-07 삼성전기주식회사 임베디드 기판 및 임베디드 기판의 제조 방법
KR20150121790A (ko) * 2014-04-21 2015-10-30 주식회사 심텍 임베디드 인쇄회로기판 및 그 제조 방법
WO2016114400A1 (ja) * 2015-01-15 2016-07-21 コニカミノルタ株式会社 配線積層構造体及び配線積層構造体の形成方法
KR20170087765A (ko) * 2016-01-21 2017-07-31 삼성전기주식회사 인쇄회로기판
WO2018003391A1 (ja) * 2016-06-29 2018-01-04 株式会社村田製作所 部品内蔵基板及びその製造方法、並びに高周波モジュール

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3942190B1 (ja) * 2006-04-25 2007-07-11 国立大学法人九州工業大学 両面電極構造の半導体装置及びその製造方法
KR100945285B1 (ko) * 2007-09-18 2010-03-03 삼성전기주식회사 전자소자 내장 인쇄회로기판 및 그 제조 방법
TWI363585B (en) * 2008-04-02 2012-05-01 Advanced Semiconductor Eng Method for manufacturing a substrate having embedded component therein
JPWO2009147936A1 (ja) * 2008-06-02 2011-10-27 イビデン株式会社 多層プリント配線板の製造方法
US20120280023A1 (en) * 2008-07-10 2012-11-08 Lsi Corporation Soldering method and related device for improved resistance to brittle fracture
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US8823160B2 (en) * 2008-08-22 2014-09-02 Stats Chippac Ltd. Integrated circuit package system having cavity
US8692135B2 (en) * 2008-08-27 2014-04-08 Nec Corporation Wiring board capable of containing functional element and method for manufacturing same
US8067306B2 (en) * 2010-02-26 2011-11-29 Stats Chippac Ltd. Integrated circuit packaging system with exposed conductor and method of manufacture thereof
CN101930956B (zh) * 2009-06-22 2013-09-25 日月光半导体制造股份有限公司 芯片封装结构及其制造方法
KR20110037332A (ko) * 2009-10-06 2011-04-13 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR101095130B1 (ko) * 2009-12-01 2011-12-16 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR101149036B1 (ko) * 2010-04-29 2012-05-24 엘지이노텍 주식회사 임베디드 인쇄회로기판용 전자부품 결합 부재 및 이를 이용한 임베디드 인쇄회로기판 및 임베디드 인쇄회로기판 제조 방법
KR101085733B1 (ko) * 2010-05-28 2011-11-21 삼성전기주식회사 전자소자 내장 인쇄회로기판 및 그 제조방법
US8847376B2 (en) * 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
KR20120026855A (ko) 2010-09-10 2012-03-20 삼성전기주식회사 임베디드 볼 그리드 어레이 기판 및 그 제조 방법
JP5772949B2 (ja) * 2011-03-24 2015-09-02 株式会社村田製作所 配線基板
KR101231286B1 (ko) * 2011-06-01 2013-02-07 엘지이노텍 주식회사 부품 내장형 인쇄회로기판 및 그 제조 방법
US20130044448A1 (en) * 2011-08-18 2013-02-21 Biotronik Se & Co. Kg Method for Mounting a Component to an Electric Circuit Board, Electric Circuit Board and Electric Circuit Board Arrangement
US9627351B2 (en) * 2012-10-22 2017-04-18 Sensor Electronic Technology, Inc. Device electrode formation using metal sheet
KR101472672B1 (ko) * 2013-04-26 2014-12-12 삼성전기주식회사 전자부품 내장 인쇄회로기판 및 그 제조방법
CN103281875A (zh) * 2013-05-28 2013-09-04 中国电子科技集团公司第十研究所 嵌入式电子线路立体组装基板的方法
US8980691B2 (en) * 2013-06-28 2015-03-17 Stats Chippac, Ltd. Semiconductor device and method of forming low profile 3D fan-out package
KR101442423B1 (ko) * 2013-08-14 2014-09-17 삼성전기주식회사 전자부품 내장기판 제조 방법 및 전자부품 내장기판
US20150197062A1 (en) * 2014-01-12 2015-07-16 Zohar SHINAR Method, device, and system of three-dimensional printing
JP5967335B2 (ja) * 2014-04-10 2016-08-10 株式会社村田製作所 部品内蔵多層基板
DE102017211330A1 (de) * 2017-07-04 2019-01-10 Siemens Aktiengesellschaft Toleranzausgleichselement für Schaltbilder
CN113645556A (zh) * 2021-08-27 2021-11-12 歌尔微电子股份有限公司 Mems麦克风封装结构及封装方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003229671A (ja) * 2001-11-30 2003-08-15 Clover Denshi Kogyo Kk 多層配線基板の製造方法
JP2004063583A (ja) * 2002-07-25 2004-02-26 Dt Circuit Technology Co Ltd 半導体装置及びその製造方法
JP2006114621A (ja) * 2004-10-13 2006-04-27 Dt Circuit Technology Co Ltd 部品内蔵配線板、部品内蔵配線板の製造方法
JP2006196785A (ja) * 2005-01-14 2006-07-27 Dainippon Printing Co Ltd 電子部品内蔵プリント配線板及びその製造方法
JP2006237526A (ja) * 2005-02-28 2006-09-07 Dainippon Printing Co Ltd 膜素子内蔵プリント配線板の製造方法、膜素子内蔵プリント配線板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3560996B2 (ja) * 1993-12-22 2004-09-02 株式会社東芝 実装用配線板およびこれを用いた実装方法
JPH08264932A (ja) * 1995-03-23 1996-10-11 Hitachi Techno Eng Co Ltd はんだバンプ形成法
CN1107979C (zh) * 1995-07-14 2003-05-07 松下电器产业株式会社 半导体器件的电极结构、形成方法及安装体和半导体器件
JP2003037205A (ja) 2001-07-23 2003-02-07 Sony Corp Icチップ内蔵多層基板及びその製造方法
JP2004335641A (ja) 2003-05-06 2004-11-25 Canon Inc 半導体素子内蔵基板の製造方法
TWI221330B (en) * 2003-08-28 2004-09-21 Phoenix Prec Technology Corp Method for fabricating thermally enhanced semiconductor device
TW200611385A (en) * 2004-09-29 2006-04-01 Phoenix Prec Technology Corp Carried structure of integrated semiconductor element and method for fabricating the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003229671A (ja) * 2001-11-30 2003-08-15 Clover Denshi Kogyo Kk 多層配線基板の製造方法
JP2004063583A (ja) * 2002-07-25 2004-02-26 Dt Circuit Technology Co Ltd 半導体装置及びその製造方法
JP2006114621A (ja) * 2004-10-13 2006-04-27 Dt Circuit Technology Co Ltd 部品内蔵配線板、部品内蔵配線板の製造方法
JP2006196785A (ja) * 2005-01-14 2006-07-27 Dainippon Printing Co Ltd 電子部品内蔵プリント配線板及びその製造方法
JP2006237526A (ja) * 2005-02-28 2006-09-07 Dainippon Printing Co Ltd 膜素子内蔵プリント配線板の製造方法、膜素子内蔵プリント配線板

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014091624A1 (ja) * 2012-12-14 2014-06-19 株式会社メイコー 部品内蔵基板および部品内蔵基板の製造方法
JP2015060912A (ja) * 2013-09-18 2015-03-30 日立化成株式会社 半導体素子搭載用パッケージ基板
KR20150102504A (ko) * 2014-02-28 2015-09-07 삼성전기주식회사 임베디드 기판 및 임베디드 기판의 제조 방법
KR102186148B1 (ko) * 2014-02-28 2020-12-03 삼성전기주식회사 임베디드 기판 및 임베디드 기판의 제조 방법
KR20150121790A (ko) * 2014-04-21 2015-10-30 주식회사 심텍 임베디드 인쇄회로기판 및 그 제조 방법
KR101630435B1 (ko) 2014-04-21 2016-06-15 주식회사 심텍 임베디드 인쇄회로기판 및 그 제조 방법
WO2016114400A1 (ja) * 2015-01-15 2016-07-21 コニカミノルタ株式会社 配線積層構造体及び配線積層構造体の形成方法
KR20170087765A (ko) * 2016-01-21 2017-07-31 삼성전기주식회사 인쇄회로기판
KR102568249B1 (ko) 2016-01-21 2023-08-18 삼성전기주식회사 인쇄회로기판
WO2018003391A1 (ja) * 2016-06-29 2018-01-04 株式会社村田製作所 部品内蔵基板及びその製造方法、並びに高周波モジュール
US10707172B2 (en) 2016-06-29 2020-07-07 Murata Manufacturing Co., Ltd. Component-embedded substrate, method of manufacturing the same, and high-frequency module

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