JP2008182231A5 - - Google Patents

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Publication number
JP2008182231A5
JP2008182231A5 JP2008010913A JP2008010913A JP2008182231A5 JP 2008182231 A5 JP2008182231 A5 JP 2008182231A5 JP 2008010913 A JP2008010913 A JP 2008010913A JP 2008010913 A JP2008010913 A JP 2008010913A JP 2008182231 A5 JP2008182231 A5 JP 2008182231A5
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JP
Japan
Prior art keywords
pin
memory
base chip
pins
configuration change
Prior art date
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Granted
Application number
JP2008010913A
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English (en)
Japanese (ja)
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JP2008182231A (ja
JP5235425B2 (ja
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Publication date
Priority claimed from KR1020070007684A external-priority patent/KR100852187B1/ko
Application filed filed Critical
Publication of JP2008182231A publication Critical patent/JP2008182231A/ja
Publication of JP2008182231A5 publication Critical patent/JP2008182231A5/ja
Application granted granted Critical
Publication of JP5235425B2 publication Critical patent/JP5235425B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2008010913A 2007-01-25 2008-01-21 効果的なシステムインパッケージ構成のためのピン構成変更回路 Expired - Fee Related JP5235425B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020070007684A KR100852187B1 (ko) 2007-01-25 2007-01-25 효과적인 시스템 인 패키지 구성을 위한 핀 구성 변경 회로
KR10-2007-0007684 2007-01-25

Publications (3)

Publication Number Publication Date
JP2008182231A JP2008182231A (ja) 2008-08-07
JP2008182231A5 true JP2008182231A5 (https=) 2011-03-10
JP5235425B2 JP5235425B2 (ja) 2013-07-10

Family

ID=39725852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008010913A Expired - Fee Related JP5235425B2 (ja) 2007-01-25 2008-01-21 効果的なシステムインパッケージ構成のためのピン構成変更回路

Country Status (4)

Country Link
US (1) US7729152B2 (https=)
JP (1) JP5235425B2 (https=)
KR (1) KR100852187B1 (https=)
TW (1) TW200832667A (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100108697A (ko) 2009-03-30 2010-10-08 삼성전자주식회사 데이터 출력 패드들의 스왑 기능을 갖는 반도체 메모리 장치
US8782336B2 (en) * 2010-05-11 2014-07-15 Marvell World Trade Ltd. Hybrid storage system with control module embedded solid-state memory
KR20120086952A (ko) * 2011-01-27 2012-08-06 에스케이하이닉스 주식회사 반도체 메모리칩 및 이를 이용한 멀티칩 패키지
JP6315185B2 (ja) * 2014-03-25 2018-04-25 セイコーエプソン株式会社 物理量検出用回路、物理量検出装置、電子機器及び移動体
US20220102333A1 (en) * 2020-09-29 2022-03-31 Alibaba Group Holding Limited Configurable computer memory architecture

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5835395A (en) * 1991-02-07 1998-11-10 Texas Instruments Incorporated Eprom pinout option
US5724281A (en) 1996-01-31 1998-03-03 Kabushiki Kaisha Toshiba Semiconductor integrated circuit having improved wiring in input terminal
US6160718A (en) * 1998-12-08 2000-12-12 Viking Components Multi-chip package with stacked chips and interconnect bumps
JP3813758B2 (ja) * 1999-04-12 2006-08-23 エルピーダメモリ株式会社 半導体記憶装置
US6632705B1 (en) * 1999-10-13 2003-10-14 Samsung Electronics Co., Ltd. Memory modules and packages using different orientations and terminal assignments
JP4151241B2 (ja) 2001-06-28 2008-09-17 横河電機株式会社 半導体試験装置のピンレジスタ回路
KR100458869B1 (ko) * 2002-04-17 2004-12-03 삼성전자주식회사 부착 방향이 자유로운 반도체 칩 패키지
JP4025584B2 (ja) 2002-05-31 2007-12-19 エルピーダメモリ株式会社 半導体記憶装置
US6876562B2 (en) * 2002-10-17 2005-04-05 Micron Technology, Inc. Apparatus and method for mounting microelectronic devices on a mirrored board assembly
JP2005243132A (ja) * 2004-02-26 2005-09-08 Renesas Technology Corp 半導体装置
JP4674850B2 (ja) * 2005-02-25 2011-04-20 ルネサスエレクトロニクス株式会社 半導体装置
US7633764B2 (en) * 2005-04-27 2009-12-15 Broadcom Corporation Ball grid array configuration for reducing path distances
JP2007193923A (ja) * 2006-01-23 2007-08-02 Fujitsu Ltd 半導体デバイス

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