TW200832667A - Pin configuration changing circuit, base chip and system in package including the same - Google Patents

Pin configuration changing circuit, base chip and system in package including the same Download PDF

Info

Publication number
TW200832667A
TW200832667A TW097101173A TW97101173A TW200832667A TW 200832667 A TW200832667 A TW 200832667A TW 097101173 A TW097101173 A TW 097101173A TW 97101173 A TW97101173 A TW 97101173A TW 200832667 A TW200832667 A TW 200832667A
Authority
TW
Taiwan
Prior art keywords
pin
memory
wafer
pins
internal
Prior art date
Application number
TW097101173A
Other languages
English (en)
Chinese (zh)
Inventor
Jin-Kwon Park
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200832667A publication Critical patent/TW200832667A/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
TW097101173A 2007-01-25 2008-01-11 Pin configuration changing circuit, base chip and system in package including the same TW200832667A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070007684A KR100852187B1 (ko) 2007-01-25 2007-01-25 효과적인 시스템 인 패키지 구성을 위한 핀 구성 변경 회로

Publications (1)

Publication Number Publication Date
TW200832667A true TW200832667A (en) 2008-08-01

Family

ID=39725852

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097101173A TW200832667A (en) 2007-01-25 2008-01-11 Pin configuration changing circuit, base chip and system in package including the same

Country Status (4)

Country Link
US (1) US7729152B2 (https=)
JP (1) JP5235425B2 (https=)
KR (1) KR100852187B1 (https=)
TW (1) TW200832667A (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100108697A (ko) 2009-03-30 2010-10-08 삼성전자주식회사 데이터 출력 패드들의 스왑 기능을 갖는 반도체 메모리 장치
US8782336B2 (en) * 2010-05-11 2014-07-15 Marvell World Trade Ltd. Hybrid storage system with control module embedded solid-state memory
KR20120086952A (ko) * 2011-01-27 2012-08-06 에스케이하이닉스 주식회사 반도체 메모리칩 및 이를 이용한 멀티칩 패키지
JP6315185B2 (ja) * 2014-03-25 2018-04-25 セイコーエプソン株式会社 物理量検出用回路、物理量検出装置、電子機器及び移動体
US20220102333A1 (en) * 2020-09-29 2022-03-31 Alibaba Group Holding Limited Configurable computer memory architecture

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5835395A (en) * 1991-02-07 1998-11-10 Texas Instruments Incorporated Eprom pinout option
US5724281A (en) 1996-01-31 1998-03-03 Kabushiki Kaisha Toshiba Semiconductor integrated circuit having improved wiring in input terminal
US6160718A (en) * 1998-12-08 2000-12-12 Viking Components Multi-chip package with stacked chips and interconnect bumps
JP3813758B2 (ja) * 1999-04-12 2006-08-23 エルピーダメモリ株式会社 半導体記憶装置
US6632705B1 (en) * 1999-10-13 2003-10-14 Samsung Electronics Co., Ltd. Memory modules and packages using different orientations and terminal assignments
JP4151241B2 (ja) 2001-06-28 2008-09-17 横河電機株式会社 半導体試験装置のピンレジスタ回路
KR100458869B1 (ko) * 2002-04-17 2004-12-03 삼성전자주식회사 부착 방향이 자유로운 반도체 칩 패키지
JP4025584B2 (ja) 2002-05-31 2007-12-19 エルピーダメモリ株式会社 半導体記憶装置
US6876562B2 (en) * 2002-10-17 2005-04-05 Micron Technology, Inc. Apparatus and method for mounting microelectronic devices on a mirrored board assembly
JP2005243132A (ja) * 2004-02-26 2005-09-08 Renesas Technology Corp 半導体装置
JP4674850B2 (ja) * 2005-02-25 2011-04-20 ルネサスエレクトロニクス株式会社 半導体装置
US7633764B2 (en) * 2005-04-27 2009-12-15 Broadcom Corporation Ball grid array configuration for reducing path distances
JP2007193923A (ja) * 2006-01-23 2007-08-02 Fujitsu Ltd 半導体デバイス

Also Published As

Publication number Publication date
JP2008182231A (ja) 2008-08-07
KR100852187B1 (ko) 2008-08-13
JP5235425B2 (ja) 2013-07-10
US7729152B2 (en) 2010-06-01
KR20080070093A (ko) 2008-07-30
US20080212351A1 (en) 2008-09-04

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