JP2008027544A5 - - Google Patents
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- Publication number
- JP2008027544A5 JP2008027544A5 JP2006200540A JP2006200540A JP2008027544A5 JP 2008027544 A5 JP2008027544 A5 JP 2008027544A5 JP 2006200540 A JP2006200540 A JP 2006200540A JP 2006200540 A JP2006200540 A JP 2006200540A JP 2008027544 A5 JP2008027544 A5 JP 2008027544A5
- Authority
- JP
- Japan
- Prior art keywords
- bit line
- sub
- complementary
- semiconductor memory
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006200540A JP2008027544A (ja) | 2006-07-24 | 2006-07-24 | 半導体記憶装置及びそのテスト方法 |
| US11/826,566 US7471579B2 (en) | 2006-07-24 | 2007-07-17 | Semiconductor memory and test method for the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006200540A JP2008027544A (ja) | 2006-07-24 | 2006-07-24 | 半導体記憶装置及びそのテスト方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008027544A JP2008027544A (ja) | 2008-02-07 |
| JP2008027544A5 true JP2008027544A5 (enExample) | 2010-11-11 |
Family
ID=38971306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006200540A Pending JP2008027544A (ja) | 2006-07-24 | 2006-07-24 | 半導体記憶装置及びそのテスト方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7471579B2 (enExample) |
| JP (1) | JP2008027544A (enExample) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5651292B2 (ja) * | 2008-04-24 | 2015-01-07 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体記憶装置及びそのテスト方法 |
| US9208902B2 (en) * | 2008-10-31 | 2015-12-08 | Texas Instruments Incorporated | Bitline leakage detection in memories |
| KR101069674B1 (ko) * | 2009-06-08 | 2011-10-04 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 이의 테스트 방법 |
| US8363450B2 (en) | 2009-07-13 | 2013-01-29 | Seagate Technology Llc | Hierarchical cross-point array of non-volatile memory |
| US8098507B2 (en) * | 2009-07-13 | 2012-01-17 | Seagate Technology Llc | Hierarchical cross-point array of non-volatile memory |
| JP2012178199A (ja) * | 2011-02-25 | 2012-09-13 | Elpida Memory Inc | 半導体装置及びその制御方法 |
| JP2012203977A (ja) * | 2011-03-28 | 2012-10-22 | Elpida Memory Inc | 半導体装置及びその制御方法並びにその情報処理システム |
| CN111161785A (zh) * | 2019-12-31 | 2020-05-15 | 展讯通信(上海)有限公司 | 静态随机存储器及其故障检测电路 |
| EP4012711A4 (en) * | 2020-10-13 | 2022-11-16 | Changxin Memory Technologies, Inc. | DATA WRITING METHOD |
| CN115620767B (zh) * | 2021-07-12 | 2025-06-06 | 长鑫存储技术有限公司 | 存储器的检测方法和存储器的检测装置 |
| US11594275B2 (en) * | 2021-07-12 | 2023-02-28 | Changxin Memory Technologies, Inc. | Method for detecting leakage position in memory and device for detecting leakage position in memory |
| US11978504B2 (en) | 2022-03-23 | 2024-05-07 | Changxin Memory Technologies, Inc. | Method and apparatus for determining sense boundary of sense amplifier, medium, and device |
| US11798617B2 (en) | 2022-03-23 | 2023-10-24 | Changxin Memory Technologies, Inc. | Method and apparatus for determining sense boundary of sense amplifier, medium, and device |
| CN116844618A (zh) * | 2022-03-23 | 2023-10-03 | 长鑫存储技术有限公司 | 存储器测试方法及装置、介质及设备 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2543870B2 (ja) * | 1986-09-30 | 1996-10-16 | 株式会社東芝 | 半導体記憶装置 |
| JP3672946B2 (ja) * | 1993-11-30 | 2005-07-20 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| US5701269A (en) * | 1994-11-28 | 1997-12-23 | Fujitsu Limited | Semiconductor memory with hierarchical bit lines |
| JPH08195100A (ja) * | 1995-01-18 | 1996-07-30 | Mitsubishi Electric Corp | 半導体記憶装置の動作テスト方法および半導体記憶装置 |
| US5748538A (en) * | 1996-06-17 | 1998-05-05 | Aplus Integrated Circuits, Inc. | OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array |
| US6327202B1 (en) * | 2000-08-25 | 2001-12-04 | Micron Technology, Inc. | Bit line pre-charge in a memory |
| JP3845051B2 (ja) * | 2002-09-11 | 2006-11-15 | 株式会社東芝 | 不揮発性半導体メモリ |
-
2006
- 2006-07-24 JP JP2006200540A patent/JP2008027544A/ja active Pending
-
2007
- 2007-07-17 US US11/826,566 patent/US7471579B2/en not_active Expired - Fee Related
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