JP2008016024A - キャッシュされたデータのダイナミック適応フラッシング - Google Patents

キャッシュされたデータのダイナミック適応フラッシング Download PDF

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Publication number
JP2008016024A
JP2008016024A JP2007172478A JP2007172478A JP2008016024A JP 2008016024 A JP2008016024 A JP 2008016024A JP 2007172478 A JP2007172478 A JP 2007172478A JP 2007172478 A JP2007172478 A JP 2007172478A JP 2008016024 A JP2008016024 A JP 2008016024A
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Japan
Prior art keywords
write
data
back data
cache memory
storage array
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JP2007172478A
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Japanese (ja)
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JP2008016024A5 (enExample
Inventor
Clark E Lubbers
イー．レッベルス クラーク
Michael D Walker
ディー．ウォーカー マイケル
David P Decenzo
ピー．デセンゾ デーヴィッド
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Seagate Technology LLC
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Seagate Technology LLC
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Publication of JP2008016024A publication Critical patent/JP2008016024A/ja
Publication of JP2008016024A5 publication Critical patent/JP2008016024A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/26—Using a specific storage system architecture
    • G06F2212/261—Storage comprising a plurality of storage devices
    • G06F2212/262—Storage comprising a plurality of storage devices configured as RAID
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2007172478A 2006-06-30 2007-06-29 キャッシュされたデータのダイナミック適応フラッシング Pending JP2008016024A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/480,128 US8234457B2 (en) 2006-06-30 2006-06-30 Dynamic adaptive flushing of cached data

Publications (2)

Publication Number Publication Date
JP2008016024A true JP2008016024A (ja) 2008-01-24
JP2008016024A5 JP2008016024A5 (enExample) 2010-08-05

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JP2007172478A Pending JP2008016024A (ja) 2006-06-30 2007-06-29 キャッシュされたデータのダイナミック適応フラッシング

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US (1) US8234457B2 (enExample)
JP (1) JP2008016024A (enExample)

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WO2008149657A1 (ja) * 2007-06-05 2008-12-11 Nec Corporation 入出力制御システム、入出力制御方法、及び、入出力制御プログラム
US8843691B2 (en) * 2008-06-25 2014-09-23 Stec, Inc. Prioritized erasure of data blocks in a flash storage device
US8924387B2 (en) * 2009-09-29 2014-12-30 Cleversafe, Inc. Social networking utilizing a dispersed storage network
US9081686B2 (en) * 2012-11-19 2015-07-14 Vmware, Inc. Coordinated hypervisor staging of I/O data for storage devices on external cache devices
WO2014122320A2 (de) * 2013-02-11 2014-08-14 Dspace Digital Signal Processing And Control Engineering Gmbh Verändern eines signalwerts eines fpga zur laufzeit
EP2765528B1 (de) 2013-02-11 2018-11-14 dSPACE digital signal processing and control engineering GmbH Wahlfreier Zugriff auf Signalwerte eines FPGA zur Laufzeit
CN110058786B (zh) * 2018-01-18 2022-12-02 伊姆西Ip控股有限责任公司 用于控制存储系统中的写请求的方法、装置和计算机程序产品
US12298912B1 (en) * 2023-11-14 2025-05-13 Qualcomm Incorporated Enhanced write buffer flush scheme for memory devices with high density storage memory architecture

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JPS6391761A (ja) * 1986-10-06 1988-04-22 Alps Electric Co Ltd キヤツシユメモリ制御方法
JPH05100954A (ja) * 1991-10-09 1993-04-23 Hokkaido Nippon Denki Software Kk キヤツシユバツフア処理制御方式
JPH06124596A (ja) * 1991-11-28 1994-05-06 Hitachi Ltd フラッシュメモリを使用した記憶装置
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US8234457B2 (en) 2012-07-31
US20080005478A1 (en) 2008-01-03

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