WO2008149657A1 - 入出力制御システム、入出力制御方法、及び、入出力制御プログラム - Google Patents

入出力制御システム、入出力制御方法、及び、入出力制御プログラム Download PDF

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Publication number
WO2008149657A1
WO2008149657A1 PCT/JP2008/059119 JP2008059119W WO2008149657A1 WO 2008149657 A1 WO2008149657 A1 WO 2008149657A1 JP 2008059119 W JP2008059119 W JP 2008059119W WO 2008149657 A1 WO2008149657 A1 WO 2008149657A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
data
storage region
control
storage
Prior art date
Application number
PCT/JP2008/059119
Other languages
English (en)
French (fr)
Inventor
Satoshi Uchida
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2009517771A priority Critical patent/JP5158576B2/ja
Priority to US12/663,201 priority patent/US8239634B2/en
Publication of WO2008149657A1 publication Critical patent/WO2008149657A1/ja

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/31—Providing disk cache in a specific location of a storage system
    • G06F2212/311—In host system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Programmable Controllers (AREA)

Abstract

　入出力制御システムは、第１及び第２記憶領域を具備し、第１記憶領域の一部または全部をキャッシュとして入出力処理を行う。第２記憶領域に入出力するデータを第１記憶領域のキャッシュとして用いる第３記憶領域へ記憶するキャッシュ管理部１１０と、第３記憶領域へ記憶されたデータの領域であるデータ領域と入出力に関する情報とを関連付けて記憶する入出力特定情報記憶部１１１と、第３記憶領域のデータ領域から第２記憶領域へのデータの出力要求を生成するライトバック部１２０と、入出力特定情報記憶部を参照して生成された出力要求の対象であるデータのデータ領域に関連付けられた入出力に関する情報を、特定する入出力特定部１００とを備える。
PCT/JP2008/059119 2007-06-05 2008-05-19 入出力制御システム、入出力制御方法、及び、入出力制御プログラム WO2008149657A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009517771A JP5158576B2 (ja) 2007-06-05 2008-05-19 入出力制御システム、入出力制御方法、及び、入出力制御プログラム
US12/663,201 US8239634B2 (en) 2007-06-05 2008-05-19 Input/output control based on information specifying input/output issuing source and input/output priority

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007149489 2007-06-05
JP2007-149489 2007-06-05

Publications (1)

Publication Number Publication Date
WO2008149657A1 true WO2008149657A1 (ja) 2008-12-11

Family

ID=40093482

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/059119 WO2008149657A1 (ja) 2007-06-05 2008-05-19 入出力制御システム、入出力制御方法、及び、入出力制御プログラム

Country Status (3)

Country Link
US (1) US8239634B2 (ja)
JP (1) JP5158576B2 (ja)
WO (1) WO2008149657A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2278470A1 (en) * 2009-07-13 2011-01-26 Fujitsu Limited Memory system and information processing device
JP2020170458A (ja) * 2019-04-05 2020-10-15 富士通株式会社 情報処理装置、制御プログラム、及び制御方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104461931B (zh) * 2014-08-18 2018-04-27 记忆科技(深圳)有限公司 多核存储装置及多核环境的跟踪日志输出处理方法
JP6653710B2 (ja) * 2015-10-02 2020-02-26 株式会社日立製作所 計算機および計算機の制御方法
US10482632B2 (en) 2017-04-28 2019-11-19 Uih America, Inc. System and method for image reconstruction

Citations (3)

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Publication number Priority date Publication date Assignee Title
JPH05128002A (ja) * 1991-11-01 1993-05-25 Fujitsu Ltd キヤツシユメモリ分割制御方式
JPH0895896A (ja) * 1994-09-27 1996-04-12 Matsushita Electric Ind Co Ltd 情報記録再生装置用上位接続制御装置
JP2007094995A (ja) * 2005-09-30 2007-04-12 Fujitsu Ltd ディスク記憶装置及びディスク記憶装置のキャッシュ制御方法

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Publication number Priority date Publication date Assignee Title
JPH03265958A (ja) 1990-03-15 1991-11-27 Nec Corp 入出力優先度変更方式
JPH06119282A (ja) * 1992-10-05 1994-04-28 Mitsubishi Electric Corp デバイス制御装置及びその優先処理方式
JPH08328956A (ja) 1995-05-30 1996-12-13 Toshiba Corp マルチプロセッサシステムのメモリ管理方式
EP1061449A4 (en) 1998-02-04 2005-12-21 Hitachi Ltd METHOD OF MANAGING ANEMATORY DISK, DISC STRUCTURE AND MEMORY
JPH11265262A (ja) 1998-03-18 1999-09-28 Hitachi Ltd 高速ライトキャッシュディスク装置
JP3506024B2 (ja) 1998-12-10 2004-03-15 日本電気株式会社 情報処理装置
JP2001109661A (ja) * 1999-10-14 2001-04-20 Hitachi Ltd キャッシュメモリの割当方法及びオペレーティングシステム及びそのオペレーティングシステムを有するコンピュータシステム
US7062609B1 (en) * 2001-09-19 2006-06-13 Cisco Technology, Inc. Method and apparatus for selecting transfer types
JP4429780B2 (ja) * 2004-03-31 2010-03-10 富士通株式会社 記憶制御装置、制御方法、および制御プログラム。
JP2005301638A (ja) * 2004-04-12 2005-10-27 Hitachi Ltd ディスクアレイ装置及びディスクアレイ装置のリザーブ解除制御方法
JP4230410B2 (ja) * 2004-05-11 2009-02-25 株式会社日立製作所 仮想ストレージの通信品質制御装置
US8279886B2 (en) * 2004-12-30 2012-10-02 Intel Corporation Dataport and methods thereof
US7337280B2 (en) * 2005-02-10 2008-02-26 International Business Machines Corporation Data processing system and method for efficient L3 cache directory management
JP4435705B2 (ja) * 2005-03-14 2010-03-24 富士通株式会社 記憶装置、その制御方法及びプログラム
JP2006350780A (ja) 2005-06-17 2006-12-28 Hitachi Ltd キャッシュ割当制御方法
US8234457B2 (en) * 2006-06-30 2012-07-31 Seagate Technology Llc Dynamic adaptive flushing of cached data
US20080065718A1 (en) * 2006-09-12 2008-03-13 Emc Corporation Configuring a cache prefetch policy that is controllable based on individual requests
US7949834B2 (en) * 2007-01-24 2011-05-24 Qualcomm Incorporated Method and apparatus for setting cache policies in a processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05128002A (ja) * 1991-11-01 1993-05-25 Fujitsu Ltd キヤツシユメモリ分割制御方式
JPH0895896A (ja) * 1994-09-27 1996-04-12 Matsushita Electric Ind Co Ltd 情報記録再生装置用上位接続制御装置
JP2007094995A (ja) * 2005-09-30 2007-04-12 Fujitsu Ltd ディスク記憶装置及びディスク記憶装置のキャッシュ制御方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2278470A1 (en) * 2009-07-13 2011-01-26 Fujitsu Limited Memory system and information processing device
US8473675B2 (en) 2009-07-13 2013-06-25 Fujitsu Limited Memory system and information processing device
JP2020170458A (ja) * 2019-04-05 2020-10-15 富士通株式会社 情報処理装置、制御プログラム、及び制御方法

Also Published As

Publication number Publication date
JPWO2008149657A1 (ja) 2010-08-26
US8239634B2 (en) 2012-08-07
US20100174871A1 (en) 2010-07-08
JP5158576B2 (ja) 2013-03-06

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