JP2007528123A - 高さが異なる隆起したドレインおよびソース領域を有するトランジスタを形成するための先進技術 - Google Patents

高さが異なる隆起したドレインおよびソース領域を有するトランジスタを形成するための先進技術 Download PDF

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Publication number
JP2007528123A
JP2007528123A JP2006537994A JP2006537994A JP2007528123A JP 2007528123 A JP2007528123 A JP 2007528123A JP 2006537994 A JP2006537994 A JP 2006537994A JP 2006537994 A JP2006537994 A JP 2006537994A JP 2007528123 A JP2007528123 A JP 2007528123A
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semiconductor
region
regions
epitaxial growth
semiconductor region
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JP2006537994A
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Japanese (ja)
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JP2007528123A5 (ko
Inventor
ファン ベントゥム ラルフ
ルーニン スコット
カムラー トルシュテン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Priority claimed from DE10351008A external-priority patent/DE10351008B4/de
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2007528123A publication Critical patent/JP2007528123A/ja
Publication of JP2007528123A5 publication Critical patent/JP2007528123A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
JP2006537994A 2003-10-31 2004-09-17 高さが異なる隆起したドレインおよびソース領域を有するトランジスタを形成するための先進技術 Pending JP2007528123A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10351008A DE10351008B4 (de) 2003-10-31 2003-10-31 Verfahren zur Herstellung von Transistoren mit erhöhten Drain- und Sourcegebieten mit unterschiedlicher Höhe sowie ein Halbleiterbauelement
US10/862,518 US7176110B2 (en) 2003-10-31 2004-06-07 Technique for forming transistors having raised drain and source regions with different heights
PCT/US2004/031038 WO2005045924A1 (en) 2003-10-31 2004-09-17 An advanced technique for forming transistors having raised drain and source regions with different height

Publications (2)

Publication Number Publication Date
JP2007528123A true JP2007528123A (ja) 2007-10-04
JP2007528123A5 JP2007528123A5 (ko) 2007-11-22

Family

ID=34575412

Family Applications (1)

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JP2006537994A Pending JP2007528123A (ja) 2003-10-31 2004-09-17 高さが異なる隆起したドレインおよびソース領域を有するトランジスタを形成するための先進技術

Country Status (4)

Country Link
JP (1) JP2007528123A (ko)
KR (1) KR101130331B1 (ko)
GB (1) GB2422488B (ko)
WO (1) WO2005045924A1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009500823A (ja) * 2005-06-30 2009-01-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド コンタクト絶縁層および異なる特性を有するシリサイド領域を形成するための技法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060252191A1 (en) * 2005-05-03 2006-11-09 Advanced Micro Devices, Inc. Methodology for deposition of doped SEG for raised source/drain regions

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124327A (ja) * 1998-10-14 2000-04-28 Toshiba Corp 半導体装置及びその製造方法
JP2002231908A (ja) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp 半導体装置の製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US616582A (en) * 1898-12-27 Victor odqtjist and john c
US690636A (en) * 1900-12-19 1902-01-07 Joseph Coldwell Warp stop-motion for looms.
US5030582A (en) * 1988-10-14 1991-07-09 Matsushita Electric Industrial Co., Ltd. Method of fabricating a CMOS semiconductor device
JP2964925B2 (ja) * 1994-10-12 1999-10-18 日本電気株式会社 相補型ｍｉｓ型ｆｅｔの製造方法
US6235568B1 (en) * 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication
TW497120B (en) * 2000-03-06 2002-08-01 Toshiba Corp Transistor, semiconductor device and manufacturing method of semiconductor device
JP2002026313A (ja) * 2000-07-06 2002-01-25 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2002043567A (ja) * 2000-07-27 2002-02-08 Mitsubishi Electric Corp 半導体装置およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124327A (ja) * 1998-10-14 2000-04-28 Toshiba Corp 半導体装置及びその製造方法
JP2002231908A (ja) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009500823A (ja) * 2005-06-30 2009-01-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド コンタクト絶縁層および異なる特性を有するシリサイド領域を形成するための技法

Also Published As

Publication number Publication date
GB2422488B (en) 2008-02-13
GB2422488A (en) 2006-07-26
KR20060108641A (ko) 2006-10-18
KR101130331B1 (ko) 2012-03-27
WO2005045924A1 (en) 2005-05-19
GB0607742D0 (en) 2006-05-31

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