JP2007520891A - ローカルｓｏｉを備えた半導体装置を形成するための方法 - Google Patents

ローカルｓｏｉを備えた半導体装置を形成するための方法 Download PDF

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JP2007520891A
JP2007520891A JP2006552133A JP2006552133A JP2007520891A JP 2007520891 A JP2007520891 A JP 2007520891A JP 2006552133 A JP2006552133 A JP 2006552133A JP 2006552133 A JP2006552133 A JP 2006552133A JP 2007520891 A JP2007520891 A JP 2007520891A
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layer
silicon
semiconductor
oxygen
rich
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JP2007520891A5 (enExample
Inventor
ケイ． オルウォフスキ、マリウス
オー． アデトゥトゥ、オルブンミ
エル． バール、アレキサンダー
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
JP2006552133A 2004-02-04 2005-01-12 ローカルｓｏｉを備えた半導体装置を形成するための方法 Pending JP2007520891A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/771,855 US7045432B2 (en) 2004-02-04 2004-02-04 Method for forming a semiconductor device with local semiconductor-on-insulator (SOI)
PCT/US2005/001534 WO2005076795A2 (en) 2004-02-04 2005-01-12 Method for forming a semiconductor device with local semiconductor-on- insulator (soi)

Publications (2)

Publication Number Publication Date
JP2007520891A true JP2007520891A (ja) 2007-07-26
JP2007520891A5 JP2007520891A5 (enExample) 2008-02-14

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JP2006552133A Pending JP2007520891A (ja) 2004-02-04 2005-01-12 ローカルｓｏｉを備えた半導体装置を形成するための方法

Country Status (5)

Country Link
US (1) US7045432B2 (enExample)
JP (1) JP2007520891A (enExample)
KR (1) KR20060130166A (enExample)
CN (1) CN1914718A (enExample)
WO (1) WO2005076795A2 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008263025A (ja) * 2007-04-11 2008-10-30 Shin Etsu Handotai Co Ltd 半導体基板の製造方法
JP2012253381A (ja) * 2012-08-22 2012-12-20 Renesas Electronics Corp 半導体装置

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CN100431103C (zh) * 2003-07-30 2008-11-05 因芬尼昂技术股份公司 高k介电膜,及其形成方法和相关的半导体器件
US7132338B2 (en) * 2003-10-10 2006-11-07 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process
US7166528B2 (en) 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US7078302B2 (en) * 2004-02-23 2006-07-18 Applied Materials, Inc. Gate electrode dopant activation method for semiconductor manufacturing including a laser anneal
JP4434832B2 (ja) * 2004-05-20 2010-03-17 Ｏｋｉセミコンダクタ株式会社 半導体装置、及びその製造方法
US7115955B2 (en) * 2004-07-30 2006-10-03 International Business Machines Corporation Semiconductor device having a strained raised source/drain
US7253493B2 (en) * 2004-08-24 2007-08-07 Micron Technology, Inc. High density access transistor having increased channel width and methods of fabricating such devices
US7226833B2 (en) * 2004-10-29 2007-06-05 Freescale Semiconductor, Inc. Semiconductor device structure and method therefor
US7560352B2 (en) * 2004-12-01 2009-07-14 Applied Materials, Inc. Selective deposition
US7682940B2 (en) 2004-12-01 2010-03-23 Applied Materials, Inc. Use of Cl2 and/or HCl during silicon epitaxial film formation
US7312128B2 (en) * 2004-12-01 2007-12-25 Applied Materials, Inc. Selective epitaxy process with alternating gas supply
US7282425B2 (en) * 2005-01-31 2007-10-16 International Business Machines Corporation Structure and method of integrating compound and elemental semiconductors for high-performance CMOS
US20060286774A1 (en) * 2005-06-21 2006-12-21 Applied Materials. Inc. Method for forming silicon-containing materials during a photoexcitation deposition process
US7651955B2 (en) * 2005-06-21 2010-01-26 Applied Materials, Inc. Method for forming silicon-containing materials during a photoexcitation deposition process
US7648927B2 (en) 2005-06-21 2010-01-19 Applied Materials, Inc. Method for forming silicon-containing materials during a photoexcitation deposition process
WO2007035660A1 (en) * 2005-09-20 2007-03-29 Applied Materials, Inc. Method to form a device on a soi substrate
KR100713924B1 (ko) * 2005-12-23 2007-05-07 주식회사 하이닉스반도체 돌기형 트랜지스터 및 그의 형성방법
US7674337B2 (en) * 2006-04-07 2010-03-09 Applied Materials, Inc. Gas manifolds for use during epitaxial film formation
KR100764360B1 (ko) * 2006-04-28 2007-10-08 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
DE112007001814T5 (de) 2006-07-31 2009-06-04 Applied Materials, Inc., Santa Clara Verfahren zum Bilden kohlenstoffhaltiger Siliziumepitaxieschichten
KR101369355B1 (ko) * 2006-07-31 2014-03-04 어플라이드 머티어리얼스, 인코포레이티드 에피택셜 층 형성 동안에 형태를 제어하는 방법
KR100764059B1 (ko) * 2006-09-22 2007-10-09 삼성전자주식회사 반도체 장치 및 그 형성 방법
US8334220B2 (en) * 2007-03-21 2012-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of selectively forming a silicon nitride layer
US7906381B2 (en) * 2007-07-05 2011-03-15 Stmicroelectronics S.A. Method for integrating silicon-on-nothing devices with standard CMOS devices
US7659158B2 (en) 2008-03-31 2010-02-09 Applied Materials, Inc. Atomic layer deposition processes for non-volatile memory devices
KR101561059B1 (ko) * 2008-11-20 2015-10-16 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8999798B2 (en) * 2009-12-17 2015-04-07 Applied Materials, Inc. Methods for forming NMOS EPI layers
US8957478B2 (en) * 2013-06-24 2015-02-17 International Business Machines Corporation Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer
US20160187414A1 (en) * 2014-12-30 2016-06-30 United Microelectronics Corp. Device having finfets and method for measuring resistance of the finfets thereof
CN111244023A (zh) * 2020-03-25 2020-06-05 上海安微电子有限公司 一种使用扩散型soi硅片制备的半导体器件及其制备方法
CN113948518A (zh) * 2021-09-18 2022-01-18 上海华力集成电路制造有限公司 同时提升pmos和nmos的性能的方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH034514A (ja) * 1989-06-01 1991-01-10 Clarion Co Ltd ウエハの製造方法
JPH10144607A (ja) * 1996-11-13 1998-05-29 Hitachi Ltd 半導体基板およびその製造方法ならびにそれを用いた半導体装置およびその製造方法
JP2000243946A (ja) * 1998-12-24 2000-09-08 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2001102555A (ja) * 1999-09-30 2001-04-13 Seiko Epson Corp 半導体装置、薄膜トランジスタ及びそれらの製造方法
JP2001110739A (ja) * 1999-10-08 2001-04-20 Sumitomo Metal Ind Ltd Ｓｉｍｏｘ基板及びその製造方法
JP2001210811A (ja) * 1999-11-17 2001-08-03 Denso Corp 半導体基板の製造方法
JP2002190599A (ja) * 2000-12-20 2002-07-05 Toshiba Corp 半導体装置及びその製造方法
JP2003243528A (ja) * 2002-02-13 2003-08-29 Toshiba Corp 半導体装置
JP2003347525A (ja) * 2002-05-22 2003-12-05 Samsung Electronics Co Ltd Ｓｏｉ半導体基板の形成方法及びそれにより形成されたｓｏｉ半導体基板

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Publication number Priority date Publication date Assignee Title
US6369438B1 (en) 1998-12-24 2002-04-09 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
TW478062B (en) * 2000-12-05 2002-03-01 Nat Science Council A method of surface treatment on the improvement of electrical properties for doped SiO2 films
FR2818012B1 (fr) 2000-12-12 2003-02-21 St Microelectronics Sa Dispositif semi-conducteur integre de memoire
FR2821483B1 (fr) 2001-02-28 2004-07-09 St Microelectronics Sa Procede de fabrication d'un transistor a grille isolee et a architecture du type substrat sur isolant, et transistor correspondant
US6429084B1 (en) * 2001-06-20 2002-08-06 International Business Machines Corporation MOS transistors with raised sources and drains

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH034514A (ja) * 1989-06-01 1991-01-10 Clarion Co Ltd ウエハの製造方法
JPH10144607A (ja) * 1996-11-13 1998-05-29 Hitachi Ltd 半導体基板およびその製造方法ならびにそれを用いた半導体装置およびその製造方法
JP2000243946A (ja) * 1998-12-24 2000-09-08 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2001102555A (ja) * 1999-09-30 2001-04-13 Seiko Epson Corp 半導体装置、薄膜トランジスタ及びそれらの製造方法
JP2001110739A (ja) * 1999-10-08 2001-04-20 Sumitomo Metal Ind Ltd Ｓｉｍｏｘ基板及びその製造方法
JP2001210811A (ja) * 1999-11-17 2001-08-03 Denso Corp 半導体基板の製造方法
JP2002190599A (ja) * 2000-12-20 2002-07-05 Toshiba Corp 半導体装置及びその製造方法
JP2003243528A (ja) * 2002-02-13 2003-08-29 Toshiba Corp 半導体装置
JP2003347525A (ja) * 2002-05-22 2003-12-05 Samsung Electronics Co Ltd Ｓｏｉ半導体基板の形成方法及びそれにより形成されたｓｏｉ半導体基板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008263025A (ja) * 2007-04-11 2008-10-30 Shin Etsu Handotai Co Ltd 半導体基板の製造方法
JP2012253381A (ja) * 2012-08-22 2012-12-20 Renesas Electronics Corp 半導体装置

Also Published As

Publication number Publication date
WO2005076795A3 (en) 2005-12-22
KR20060130166A (ko) 2006-12-18
US20050170604A1 (en) 2005-08-04
CN1914718A (zh) 2007-02-14
US7045432B2 (en) 2006-05-16
WO2005076795A2 (en) 2005-08-25

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