JP2007518270A5 - - Google Patents

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Publication number
JP2007518270A5
JP2007518270A5 JP2006549310A JP2006549310A JP2007518270A5 JP 2007518270 A5 JP2007518270 A5 JP 2007518270A5 JP 2006549310 A JP2006549310 A JP 2006549310A JP 2006549310 A JP2006549310 A JP 2006549310A JP 2007518270 A5 JP2007518270 A5 JP 2007518270A5
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JP
Japan
Prior art keywords
fin
forming
gate
trench
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006549310A
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English (en)
Japanese (ja)
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JP5270093B2 (ja
JP2007518270A (ja
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Publication date
Priority claimed from US10/754,559 external-priority patent/US7041542B2/en
Application filed filed Critical
Publication of JP2007518270A publication Critical patent/JP2007518270A/ja
Publication of JP2007518270A5 publication Critical patent/JP2007518270A5/ja
Application granted granted Critical
Publication of JP5270093B2 publication Critical patent/JP5270093B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2006549310A 2004-01-12 2004-12-21 ダマシンプロセスにより形成されるトライゲートＦｉｎＦＥＴ Expired - Lifetime JP5270093B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/754,559 2004-01-12
US10/754,559 US7041542B2 (en) 2004-01-12 2004-01-12 Damascene tri-gate FinFET
PCT/US2004/043104 WO2005071726A1 (en) 2004-01-12 2004-12-21 Damascene tri-gate finfet

Publications (3)

Publication Number Publication Date
JP2007518270A JP2007518270A (ja) 2007-07-05
JP2007518270A5 true JP2007518270A5 (enExample) 2008-02-14
JP5270093B2 JP5270093B2 (ja) 2013-08-21

Family

ID=34739410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006549310A Expired - Lifetime JP5270093B2 (ja) 2004-01-12 2004-12-21 ダマシンプロセスにより形成されるトライゲートＦｉｎＦＥＴ

Country Status (8)

Country Link
US (1) US7041542B2 (enExample)
JP (1) JP5270093B2 (enExample)
KR (1) KR101066270B1 (enExample)
CN (1) CN100521116C (enExample)
DE (1) DE112004002640B4 (enExample)
GB (1) GB2425656B (enExample)
TW (1) TWI370546B (enExample)
WO (1) WO2005071726A1 (enExample)

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US7442590B2 (en) * 2006-04-27 2008-10-28 Freescale Semiconductor, Inc Method for forming a semiconductor device having a fin and structure thereof
CN102217074B (zh) * 2008-09-16 2015-08-12 台湾积体电路制造股份有限公司 鳍式场效应晶体管(finfet)
US8202780B2 (en) * 2009-07-31 2012-06-19 International Business Machines Corporation Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions
US8334184B2 (en) * 2009-12-23 2012-12-18 Intel Corporation Polish to remove topography in sacrificial gate layer prior to gate patterning
US8535998B2 (en) * 2010-03-09 2013-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a gate structure
US8492214B2 (en) * 2011-03-18 2013-07-23 International Business Machines Corporation Damascene metal gate and shield structure, methods of manufacture and design structures
US8361854B2 (en) * 2011-03-21 2013-01-29 United Microelectronics Corp. Fin field-effect transistor structure and manufacturing process thereof
US8853035B2 (en) 2011-10-05 2014-10-07 International Business Machines Corporation Tucked active region without dummy poly for performance boost and variation reduction
CN103515430B (zh) * 2012-06-19 2016-08-10 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其制造方法
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US10037991B2 (en) 2014-01-09 2018-07-31 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for fabricating FinFETs with different threshold voltages
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