JP5270093B2 - ダマシンプロセスにより形成されるトライゲートＦｉｎＦＥＴ - Google Patents

ダマシンプロセスにより形成されるトライゲートＦｉｎＦＥＴ Download PDF

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JP5270093B2
JP5270093B2 JP2006549310A JP2006549310A JP5270093B2 JP 5270093 B2 JP5270093 B2 JP 5270093B2 JP 2006549310 A JP2006549310 A JP 2006549310A JP 2006549310 A JP2006549310 A JP 2006549310A JP 5270093 B2 JP5270093 B2 JP 5270093B2
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fin
forming
gate
layer
dummy
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Japanese (ja)
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JP2007518270A5 (enExample
JP2007518270A (ja
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エス． アーメッド シブリー
ワン ハイホン
ユ ビン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
JP2006549310A 2004-01-12 2004-12-21 ダマシンプロセスにより形成されるトライゲートＦｉｎＦＥＴ Expired - Lifetime JP5270093B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/754,559 2004-01-12
US10/754,559 US7041542B2 (en) 2004-01-12 2004-01-12 Damascene tri-gate FinFET
PCT/US2004/043104 WO2005071726A1 (en) 2004-01-12 2004-12-21 Damascene tri-gate finfet

Publications (3)

Publication Number Publication Date
JP2007518270A JP2007518270A (ja) 2007-07-05
JP2007518270A5 JP2007518270A5 (enExample) 2008-02-14
JP5270093B2 true JP5270093B2 (ja) 2013-08-21

Family

ID=34739410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006549310A Expired - Lifetime JP5270093B2 (ja) 2004-01-12 2004-12-21 ダマシンプロセスにより形成されるトライゲートＦｉｎＦＥＴ

Country Status (8)

Country Link
US (1) US7041542B2 (enExample)
JP (1) JP5270093B2 (enExample)
KR (1) KR101066270B1 (enExample)
CN (1) CN100521116C (enExample)
DE (1) DE112004002640B4 (enExample)
GB (1) GB2425656B (enExample)
TW (1) TWI370546B (enExample)
WO (1) WO2005071726A1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7084018B1 (en) * 2004-05-05 2006-08-01 Advanced Micro Devices, Inc. Sacrificial oxide for minimizing box undercut in damascene FinFET
JP2006013303A (ja) * 2004-06-29 2006-01-12 Toshiba Corp 半導体装置及びその製造方法
US7381649B2 (en) * 2005-07-29 2008-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for a multiple-gate FET device and a method for its fabrication
US7442590B2 (en) * 2006-04-27 2008-10-28 Freescale Semiconductor, Inc Method for forming a semiconductor device having a fin and structure thereof
WO2010032174A1 (en) * 2008-09-16 2010-03-25 Nxp B.V. Fin field effect transistor (finfet)
US8202780B2 (en) * 2009-07-31 2012-06-19 International Business Machines Corporation Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions
US8334184B2 (en) * 2009-12-23 2012-12-18 Intel Corporation Polish to remove topography in sacrificial gate layer prior to gate patterning
US8535998B2 (en) * 2010-03-09 2013-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a gate structure
US8492214B2 (en) * 2011-03-18 2013-07-23 International Business Machines Corporation Damascene metal gate and shield structure, methods of manufacture and design structures
US8361854B2 (en) * 2011-03-21 2013-01-29 United Microelectronics Corp. Fin field-effect transistor structure and manufacturing process thereof
US8853035B2 (en) 2011-10-05 2014-10-07 International Business Machines Corporation Tucked active region without dummy poly for performance boost and variation reduction
CN103515430B (zh) * 2012-06-19 2016-08-10 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其制造方法
EP3050106B1 (en) * 2013-09-27 2020-11-18 Intel Corporation Low leakage non-planar access transistor for embedded dynamic random access memeory (edram)
US10037991B2 (en) * 2014-01-09 2018-07-31 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for fabricating FinFETs with different threshold voltages
US9252243B2 (en) 2014-02-07 2016-02-02 International Business Machines Corporation Gate structure integration scheme for fin field effect transistors
US9966272B1 (en) * 2017-06-26 2018-05-08 Globalfoundries Inc. Methods for nitride planarization using dielectric

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5705405A (en) * 1994-09-30 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of making the film transistor with all-around gate electrode
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
US6265256B1 (en) * 1998-09-17 2001-07-24 Advanced Micro Devices, Inc. MOS transistor with minimal overlap between gate and source/drain extensions
JP4270719B2 (ja) * 1999-06-30 2009-06-03 株式会社東芝 半導体装置及びその製造方法
US6303447B1 (en) * 2000-02-11 2001-10-16 Chartered Semiconductor Manufacturing Ltd. Method for forming an extended metal gate using a damascene process
KR100350056B1 (ko) * 2000-03-09 2002-08-24 삼성전자 주식회사 다마신 게이트 공정에서 자기정렬콘택패드 형성 방법
US6483156B1 (en) * 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
JP4058751B2 (ja) * 2000-06-20 2008-03-12 日本電気株式会社 電界効果型トランジスタの製造方法
US6342410B1 (en) * 2000-07-10 2002-01-29 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with three sided gate structure on semiconductor on insulator
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
KR100372647B1 (ko) * 2000-10-13 2003-02-19 주식회사 하이닉스반도체 다마신 금속게이트 형성방법
US6562665B1 (en) * 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6396108B1 (en) * 2000-11-13 2002-05-28 Advanced Micro Devices, Inc. Self-aligned double gate silicon-on-insulator (SOI) device
US6551885B1 (en) * 2001-02-09 2003-04-22 Advanced Micro Devices, Inc. Low temperature process for a thin film transistor
US6406951B1 (en) * 2001-02-12 2002-06-18 Advanced Micro Devices, Inc. Fabrication of fully depleted field effect transistor with raised source and drain in SOI technology
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
JP3543117B2 (ja) * 2001-03-13 2004-07-14 独立行政法人産業技術総合研究所 二重ゲート電界効果トランジスタ
FR2822293B1 (fr) * 2001-03-13 2007-03-23 Nat Inst Of Advanced Ind Scien Transistor a effet de champ et double grille, circuit integre comportant ce transistor, et procede de fabrication de ce dernier
US6458662B1 (en) * 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
US6551886B1 (en) * 2001-04-27 2003-04-22 Advanced Micro Devices, Inc. Ultra-thin body SOI MOSFET and gate-last fabrication method
US6635923B2 (en) * 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
JP2003037264A (ja) * 2001-07-24 2003-02-07 Toshiba Corp 半導体装置およびその製造方法
DE10137217A1 (de) 2001-07-30 2003-02-27 Infineon Technologies Ag Steg-Feldeffekttransistor und Verfahren zum Herstellen eines Steg-Feldeffekttransistors
US20030025167A1 (en) * 2001-07-31 2003-02-06 International Business Machines Corporation Activating in-situ doped gate on high dielectric constant materials
US6509611B1 (en) * 2001-09-21 2003-01-21 International Business Machines Corporation Method for wrapped-gate MOSFET
US6610576B2 (en) * 2001-12-13 2003-08-26 International Business Machines Corporation Method for forming asymmetric dual gate transistor
US6800905B2 (en) * 2001-12-14 2004-10-05 International Business Machines Corporation Implanted asymmetric doped polysilicon gate FinFET
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
US20030151077A1 (en) * 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
CN1191611C (zh) * 2002-04-10 2005-03-02 台湾积体电路制造股份有限公司 制作双栅极结构的方法
CN1225799C (zh) * 2002-04-24 2005-11-02 华邦电子股份有限公司 金属氧化物半导体场效应晶体管及其制造方法
EP1383164A1 (en) 2002-07-17 2004-01-21 Interuniversitair Micro-Elektronica Centrum (IMEC) FinFET device and a method for manufacturing such device
US6855990B2 (en) * 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US6645797B1 (en) * 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6764884B1 (en) 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
US6765303B1 (en) * 2003-05-06 2004-07-20 Advanced Micro Devices, Inc. FinFET-based SRAM cell
US7029958B2 (en) * 2003-11-04 2006-04-18 Advanced Micro Devices, Inc. Self aligned damascene gate

Also Published As

Publication number Publication date
US7041542B2 (en) 2006-05-09
WO2005071726A1 (en) 2005-08-04
DE112004002640T5 (de) 2007-01-04
CN100521116C (zh) 2009-07-29
GB0615272D0 (en) 2006-09-06
GB2425656A (en) 2006-11-01
TWI370546B (en) 2012-08-11
KR101066270B1 (ko) 2011-09-21
KR20060123479A (ko) 2006-12-01
GB2425656B (en) 2007-12-05
CN1902742A (zh) 2007-01-24
DE112004002640B4 (de) 2008-12-18
DE112004002640T8 (de) 2007-03-22
JP2007518270A (ja) 2007-07-05
US20050153492A1 (en) 2005-07-14
TW200529432A (en) 2005-09-01

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