JP2007305694A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP2007305694A JP2007305694A JP2006130733A JP2006130733A JP2007305694A JP 2007305694 A JP2007305694 A JP 2007305694A JP 2006130733 A JP2006130733 A JP 2006130733A JP 2006130733 A JP2006130733 A JP 2006130733A JP 2007305694 A JP2007305694 A JP 2007305694A
- Authority
- JP
- Japan
- Prior art keywords
- pedestal
- electrode
- post electrode
- semiconductor device
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05555—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
- H01L2224/13027—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being offset with respect to the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】ウエハ上の配線3に設けられる台座4bの径をポスト電極5の径より小さく形成して、台座4bがポスト電極5の下に埋没して隠れるようにした。
【選択図】図1
Description
図4は従来の半導体装置におけるポスト電極部分を示す図であって、(a)は側面図、(b)は平面図である。
図において1は図示しない集積回路が形成されたウエハのパッシペーション層上に形成された有機絶縁膜である。
3は配線で、ホトリソグラフィーによってレジストによる配線パターンを形成し、シード層2を介して供給される電流によって配線パターン内にめっきを施すことで形成される。配線3の形成後レジストは除去される。
5は台座4a上に形成された円柱状のポスト電極で、ホトリソグラフィーによってレジストによるポスト電極パターンを台座4a上に形成し、シード層2を介して供給される電流によってポスト電極パターン内にめっきを施すことで形成される。
ポスト電極5形成後、レジストは除去され、そして配線3間に露出するシード層2がエッチングされ、これにより各配線3は電気的に分離される。
6は配線3及びポスト電極5が形成された面を覆うようにモールデングされた封止樹脂で、モールデング後、ポスト電極5の頭頂部を露出させるように研削されている。
このような構成による半導体装置において、配線3の台座4aの径はポスト電極5の径より大きく設計され、平面で表わすと図4(b)のようになる。
また、配線数を確保するために配線を微細にすると形成が困難になり、かつポスト電極周囲の構造が複雑になるため、形状にばらつきが生じるという問題がある。
また、電極ポスト形成のためのレジストパターン形成時には、ホトリソグラフィーでマスク合せを行うため、マスク合わせ用の位置あわせマークをウエハ上に設けるための領域が必要となり、しかもこの位置あわせマークが最終構造で痕跡として残るという問題もある。
また、電極の形成後は、台座が電極の下に埋まるため、電極の部分は台座を含めて単純な柱状になり、台座との重ね合わせ精度による形状のばらつきがなくなるという効果も得られる。
尚従来のものと同一の部分は同一の符号を用いて説明する。
図において1は図示しない集積回路が形成されたウエハ(基板)のパッシペーション層上に形成された有機絶縁膜で、この有機絶縁膜1としてはポリイミド樹脂、BCB樹脂、PBO樹脂が用いられる。
3は台座4bを有する配線で、主として図示しない集積回路のパッドと後述するポスト電極を電気的に接続するために用いられる。この配線3としては、配線抵抗を下げるために銅が用いられるが、金、銀、アルミを用いることも可能である。
5は台座4b上に形成された円柱状のポスト電極で、このポスト電極5は半導体装置の最終的な構造において封止樹脂6(図4参照)を貫通し、外部電極である図示しないはんだ端子と配線3を電気的に接続するために形成される。
まず、半導体回路が形成されかつパッド上のパッシベーション膜が開口された状態にあるウエハを準備し、そのパッシベーション膜上に有機絶縁膜1を被覆し、パッド上のパッシベーション膜の開口部に重複して有機絶縁膜1の開口部を形成する。
次に、ウエハ全面にスパッタリングによってシード層2を形成した後、ホトリソグラフィーによってレジストによる配線パターンを形成し、シード層2を介して供給される電流によって配線パターン内にめっきを施すことで端部に台座4aを有する配線3を形成した後、レジストを除去する。
次に、ホトリソグラフィーによってレジストによるポスト電極パターンを台座4b上に形成し、シード層2を介して供給される電流によってポスト電極パターン内にめっきを施すことで台座4a上にポスト電極5を形成した後、レジストを除去する。
次に、配線3間に露出するシード層2をエッチングして、各配線3を電気的に分離する。
そして、配線3及びポスト電極5が形成された面を封止樹脂6で覆うようにウエハレベルで樹脂モールデングした後、樹脂封止面を研削してポスト電極5の頭頂部を露出させる。
このように製造された半導体装置は、ポスト電極5が封止樹脂6を貫通して外部電極であるはんだ端子と配線3とを電気的に接続した構造となっており、そしてこの配線3は上述したように台座4bと反対側の端部が有機絶縁膜1の開口部を介して図示しない集積回路のパッドと接続されているので、集積回路のパッドは、電気的に外部電極であるはんだ端子と接続されたものとなる。
台座4bの径とポスト電極5の径の差は、ホトリソグラフィーによりポスト電極5を形成する時のマスク合わせ精度より大きく設計し、これにより台座4bは、少なくともポスト電極5形成時のホトリソグラフィーで必要な重ね寸法分だけ小さく形成しているため、ポスト電極5をめっきにより形成するときにこの台座4bはポスト電極5の下に埋まり、ポスト電極5の周囲に台座4bが露出しないものとなる。
以上説明した第1の実施例によると、以下の効果が得られる。
図2は従来と実施例のポスト電極間の配線スペースを示す平面図で、(a)は従来の構造、(b)本実施例の構造である。
図3は本発明の第2の実施例を示す図であって、(a)はポスト電極形成直前の側面図、(b)はその平面図である。
1はウエハの集積回路パッシペーション層上に形成された有機絶縁膜、2はシード層である。
3はシード層2上に形成された配線、4cは配線3に設けられた台座であり、本実施例はこの台座4cをポスト電極形成のためのホトリソ加工においてマスク合わせに使用するための位置決めマークとするもので、そのため台座4cを他の台座4b(図1参照)の形状と異なるユニークな形状、例えば図3(b)に示したように十字形のパターンとして形成したものである。
このレジストパターン8は十字形に形成された台座4cが内側に収まるように形成され、このレジストパターン8内にメッキを施すことでポスト電極5(図1参照)が形成される。
以上説明したように第2の実施例では、少なくとも1つのポスト電極5の台座4cの形状を他のポスト電極の台座4bの形状と異なるユニークなパターンとすることで、ポスト電極形成のためのレジストパターン形成に使用するマスクの位置決めマークとしているため、マスク合わせのための位置決めマークを誤認識することがなくなり、また位置決めマークとして使用した台座4cは同じ材料のポスト電極下に埋没するため、位置決めマークを設けるための領域が不要で、かつ最終構造上に痕跡が残らないという効果が得られる。
以上、第1、第2の実施例について説明したが、ポスト電極5の形状や、ポスト電極下に埋没する配線3の台座4b、4cの形状は、第1、第2の実施例のものに限られるものではない。
2 シード層
3 配線
4a〜4c 台座
5 ポスト電極
6 封止樹脂
7 レジスト
8 レジストパターン
Claims (5)
- 基板上に形成された複数の配線と、
各配線の端部に形成された台座と、
各台座上に形成された電極とを備え、
前記電極は一列に配置されていて、隣り合う電極間に台座が電極から露出しないように形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記台座の径を前記電極の径より小さくしたことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記台座の径と前記電極の径の差は、ホトリソグラフィーによる電極形成時のマスク合わせ精度より大きくしたことを特徴とする半導体装置。 - 端部に台座複数の配線を基板上に形成し、各台座上に電極を形成する半導体装置の製造方法において、
複数形成される電極の少なくとも1つの電極の台座を、他の電極ポストの台座と異なる形状とし、その異なる形状の台座を位置決めマークとして、ホトリソグラフィーによる電極形成時に前記位置決めマークを基準にしてマスク合わせを行うことを特徴とする半導体装置の製造方法。 - 請求項4に記載の半導体装置の製造方法において、
前記位置決めマークとする台座の形状を十字形としたことを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006130733A JP5107529B2 (ja) | 2006-05-09 | 2006-05-09 | 半導体装置及びその製造方法 |
US11/638,550 US7652380B2 (en) | 2006-05-09 | 2006-12-14 | Semiconductor device and method of producing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006130733A JP5107529B2 (ja) | 2006-05-09 | 2006-05-09 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007305694A true JP2007305694A (ja) | 2007-11-22 |
JP5107529B2 JP5107529B2 (ja) | 2012-12-26 |
Family
ID=38684366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006130733A Expired - Fee Related JP5107529B2 (ja) | 2006-05-09 | 2006-05-09 | 半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7652380B2 (ja) |
JP (1) | JP5107529B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012190885A (ja) * | 2011-03-09 | 2012-10-04 | Teramikros Inc | 半導体装置及びその製造方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200921868A (en) * | 2007-11-07 | 2009-05-16 | Advanced Semiconductor Eng | Substrate structure |
JP5337404B2 (ja) * | 2008-05-21 | 2013-11-06 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04321250A (ja) * | 1990-10-31 | 1992-11-11 | Internatl Business Mach Corp <Ibm> | 電気的相互接続装置 |
JPH11354578A (ja) * | 1998-06-11 | 1999-12-24 | Casio Comput Co Ltd | 半導体装置及びその製造方法 |
WO2000044043A1 (fr) * | 1999-01-22 | 2000-07-27 | Hitachi, Ltd. | Dispositif a semi-conducteurs et son procede de fabrication |
JP2000228423A (ja) * | 1999-02-05 | 2000-08-15 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2002203925A (ja) * | 2000-12-28 | 2002-07-19 | Fujitsu Ltd | 外部接続端子及び半導体装置 |
JP2004319638A (ja) * | 2003-04-14 | 2004-11-11 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005116632A (ja) * | 2003-10-03 | 2005-04-28 | Rohm Co Ltd | 半導体装置の製造方法および半導体装置 |
JP2005260207A (ja) * | 2004-02-10 | 2005-09-22 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2005327816A (ja) * | 2004-05-12 | 2005-11-24 | Fujitsu Ltd | 半導体装置及びその製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09191084A (ja) * | 1996-01-10 | 1997-07-22 | Nec Corp | 半導体装置及びその製造方法 |
JP3389517B2 (ja) | 1998-12-10 | 2003-03-24 | 三洋電機株式会社 | チップサイズパッケージ及びその製造方法 |
JP4526651B2 (ja) * | 1999-08-12 | 2010-08-18 | 富士通セミコンダクター株式会社 | 半導体装置 |
US6201305B1 (en) * | 2000-06-09 | 2001-03-13 | Amkor Technology, Inc. | Making solder ball mounting pads on substrates |
JP3617647B2 (ja) * | 2002-11-08 | 2005-02-09 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
US7122458B2 (en) * | 2004-07-22 | 2006-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating pad redistribution layer |
-
2006
- 2006-05-09 JP JP2006130733A patent/JP5107529B2/ja not_active Expired - Fee Related
- 2006-12-14 US US11/638,550 patent/US7652380B2/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04321250A (ja) * | 1990-10-31 | 1992-11-11 | Internatl Business Mach Corp <Ibm> | 電気的相互接続装置 |
JPH11354578A (ja) * | 1998-06-11 | 1999-12-24 | Casio Comput Co Ltd | 半導体装置及びその製造方法 |
WO2000044043A1 (fr) * | 1999-01-22 | 2000-07-27 | Hitachi, Ltd. | Dispositif a semi-conducteurs et son procede de fabrication |
JP2000228423A (ja) * | 1999-02-05 | 2000-08-15 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2002203925A (ja) * | 2000-12-28 | 2002-07-19 | Fujitsu Ltd | 外部接続端子及び半導体装置 |
JP2004319638A (ja) * | 2003-04-14 | 2004-11-11 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005116632A (ja) * | 2003-10-03 | 2005-04-28 | Rohm Co Ltd | 半導体装置の製造方法および半導体装置 |
JP2005260207A (ja) * | 2004-02-10 | 2005-09-22 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2005327816A (ja) * | 2004-05-12 | 2005-11-24 | Fujitsu Ltd | 半導体装置及びその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012190885A (ja) * | 2011-03-09 | 2012-10-04 | Teramikros Inc | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20070262461A1 (en) | 2007-11-15 |
JP5107529B2 (ja) | 2012-12-26 |
US7652380B2 (en) | 2010-01-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7045908B2 (en) | Semiconductor device and method for manufacturing the same | |
KR100595885B1 (ko) | 반도체장치 및 그 제조방법 | |
US7586181B2 (en) | Semiconductor device and method for manufacturing | |
US10797012B2 (en) | Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices | |
JP5801989B2 (ja) | 半導体装置および半導体装置の製造方法 | |
KR20070023523A (ko) | 반도체 패키지 및 그 제조 방법 | |
US20080105981A1 (en) | Semiconductor device having projecting electrode formed by electrolytic plating, and manufacturing method thereof | |
CN103681563A (zh) | 集成电路中具有开口的金属焊盘 | |
KR101374148B1 (ko) | 반도체 패키지 및 이의 제조 방법 | |
KR100858386B1 (ko) | 반도체소자 형성용 기판 및 반도체소자의 제조방법 | |
JP5107529B2 (ja) | 半導体装置及びその製造方法 | |
US7741705B2 (en) | Semiconductor device and method of producing the same | |
JP6303137B2 (ja) | 半導体装置 | |
JP2010062170A (ja) | 半導体装置およびその製造方法 | |
JP2012033624A (ja) | ウエハレベルパッケージ構造およびその製造方法 | |
JP2009231402A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2007329508A (ja) | 半導体装置 | |
JP6305375B2 (ja) | 半導体装置および半導体装置の製造方法 | |
KR20110014962A (ko) | 반도체 장치 및 그 제조방법 | |
JP4987910B2 (ja) | 半導体素子の半田層の製造方法、半導体素子のマークの製造方法及び半導体素子のダイシング方法 | |
JP4506780B2 (ja) | 半導体基板の製造方法 | |
JP4341694B2 (ja) | 半導体素子の製造方法 | |
JP2007258354A (ja) | 半導体装置の製造方法 | |
JP2001135747A (ja) | 半導体装置の製造方法 | |
JP2006012952A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080919 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20081210 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20090127 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110525 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110531 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110729 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120403 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120703 |
|
A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20120710 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120904 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121004 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151012 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |