JP2007184362A - 積層型半導体装置及びその製造方法 - Google Patents
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- H01L2225/1047—Details of electrical connections between containers
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- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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Abstract
【解決手段】層間接続用の半田ボール2を用いたリフロー実装によって積層型に接合され、半導体チップ5,10を搭載するボールグリッドアレイ用の回路基板6,11を有する複数の半導体装置3,4を備えた積層型半導体装置1において、回路基板6の両端縁におけるチップ搭載側面両側部に基板傾斜規制用の突起8が配設されている。
【選択図】図1
Description
図1は、本発明の第1の実施の形態に係る積層型半導体装置を説明するために示す図である。図1(a)は断面図を、図1(b)はA矢視図を、図1(c)は側面図をそれぞれ示す。
図1(a)〜(c)において、符号1で示す積層型半導体装置1は、層間接続用の半田ボール2を用いたリフロー実装によって積層型に接合された2つの半導体装置3,4から大略構成されている。
半導体装置3は、回路面5Aを基板側に有する半導体チップ5と、この半導体チップ5を搭載するBGA用の回路基板(配線基板)6とを備えている。
半導体装置4は、半導体装置3と同様に回路面10Aを基板側に有する半導体チップ10と、この半導体チップ10を搭載するBGA用の回路基板(配線基板)11とを備え、半導体装置3上に接合されている。
予め絶縁基板(図示せず)に導体パターン(図示せず)を形成してなる(図2のステップS1)回路基板6,11の回路面側にそれぞれ平面略H字状の接着フィルム7と平面略矩形状の接着フィルム12を貼付する(図2のステップS2)。この場合、接着フィルム7は回路基板6のチップ搭載位置(1箇所)及び突起接着位置(4箇所)を含む領域に、また接着フィルム12はチップ搭載位置(1箇所)にそれぞれ貼付される。なお、回路基板6,11上に接着材としてそれぞれ接着フィルム7,12を貼付する場合について説明したが、これら接着フィルム7,12を貼付する代わりに接着剤を塗布してもよい。
回路基板6の突起接着位置に接着フィルム7を介して4つの突起8を配置する(図2のステップS3)。この場合、突起8の接着は、接着フィルム7の形成・接着に用いるプレス金型によってその形成と同時に実施される。
回路基板6,11の各チップ搭載位置にそれぞれ接着フィルム7,12を介して半導体チップ5,10を配置する(図2のステップS4)。この場合、半導体チップ5,10の配置は、突起8の配置前に、あるいは突起8の配置と同時に実施してもよい。
回路基板6,11上の接着フィルム7,12を硬化させる(図2のステップS5)。この場合、接着フィルム7が硬化すると、回路基板6,11の各チップ搭載側面にそれぞれ接着フィルム7と接着フィルム12を介して半導体チップ5,10が搭載されるとともに、回路基板6のチップ搭載側面に突起8が接着される。
回路基板6,11のチップ反搭載側面(ランド)にそれぞれ半田ボール9,2を搭載する。ここで、半田ボール9,2を搭載するにあたり、半導体チップ5,10の封止工程やワイヤボンディング工程を必要とする場合には、これら工程が「半導体装置の接合」の工程前に実施される(図2のステップS6)。
このようにして、積層型半導体装置1を製造することができる。
以上説明した第1の実施の形態によれば、次に示す効果が得られる。
図5は、本発明の第2の実施の形態に係る積層型半導体装置を説明するために示す図である。図5(a)は断面図を、図5(b)はB矢視図を、図5(c)は側面図をそれぞれ示す。図5(a)〜(c)において、図1(a)〜(c)と同一又は同等の部材については同一の符号を付し、詳細な説明は省略する。
以上説明した第2の実施の形態によれば、第1の実施の形態の効果(1)〜(5)に加え、次に示す効果が得られる。
第1接着フィルム52及び第2接着フィルムの平面形状は矩形であるため、その加工を簡単に行うことができる。
Claims (7)
- 層間接続用の半田ボールを用いたリフロー実装によって積層型に接合され、半導体チップを搭載するボールグリッドアレイ用の回路基板を有する複数の半導体装置を備えた積層型半導体装置において、
前記回路基板のうち互いに隣り合う2つの回路基板間に基板傾斜規制用の突起が配設されていることを特徴とする積層型半導体装置。 - 前記突起は、前記2つの回路基板のうち下方の回路基板の両端縁上面であって、前記複数の半導体装置を搬送して積層型に接合するためのリフロー炉に対する搬送側領域及び前記搬送側領域と反対側に位置する反搬送側領域に配置されている請求項1に記載の積層型半導体装置。
- 前記突起の高さは、前記2つの回路基板間に介在する前記半田ボールの高さより小さい寸法に設定されている請求項1に記載の積層型半導体装置。
- 前記突起は、前記回路基板の片側面であって前記半導体チップを搭載する側に配置されている請求項1に記載の積層型半導体装置。
- 前記突起は、絶縁性有機材料によって形成されている請求項1に記載の積層型半導体装置。
- 層間接続用の半田ボールを用いたリフロー実装によって積層型に接合され、半導体チップを搭載するボールグリッドアレイ用の回路基板を有する複数の半導体装置を備えた積層型半導体装置の製造方法において、
前記回路基板にチップ搭載用の接着材を配置する工程と、
前記回路基板に未硬化の前記接着材を介して前記半導体チップを搭載するとともに、前記回路基板のうち互いに隣り合う2つの回路基板間に基板傾斜規制用の突起を前記未硬化の接着材によって配置する工程と、
前記未硬化の接着材を硬化させる工程とを備えたことを特徴とする積層型半導体装置の製造方法。 - 絶縁性フィルムを打ち抜くことにより前記突起を複数個形成し、前記複数個の突起を前記回路基板に同時に貼り付ける請求項6に記載の積層型半導体装置の製造方法。
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JP2006000682A JP4650269B2 (ja) | 2006-01-05 | 2006-01-05 | 積層型半導体装置の製造方法 |
US11/447,975 US7626126B2 (en) | 2006-01-05 | 2006-06-07 | Multilayer semiconductor device |
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JP2006000682A JP4650269B2 (ja) | 2006-01-05 | 2006-01-05 | 積層型半導体装置の製造方法 |
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JP4650269B2 JP4650269B2 (ja) | 2011-03-16 |
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Cited By (2)
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JP2008204998A (ja) * | 2007-02-16 | 2008-09-04 | Toppan Printing Co Ltd | 高集積半導体装置 |
JP2010147090A (ja) * | 2008-12-16 | 2010-07-01 | Renesas Technology Corp | 半導体装置及びその製造方法 |
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JP2010186848A (ja) * | 2009-02-12 | 2010-08-26 | Fujitsu Ltd | 電子部品ユニットの製造方法 |
EP2309829A1 (en) * | 2009-09-24 | 2011-04-13 | Harman Becker Automotive Systems GmbH | Multilayer circuit board |
US20110084375A1 (en) * | 2009-10-13 | 2011-04-14 | Freescale Semiconductor, Inc | Semiconductor device package with integrated stand-off |
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Cited By (3)
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JP2008204998A (ja) * | 2007-02-16 | 2008-09-04 | Toppan Printing Co Ltd | 高集積半導体装置 |
JP2010147090A (ja) * | 2008-12-16 | 2010-07-01 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US8648453B2 (en) | 2008-12-16 | 2014-02-11 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing the same |
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US7626126B2 (en) | 2009-12-01 |
JP4650269B2 (ja) | 2011-03-16 |
US20070151754A1 (en) | 2007-07-05 |
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