JP2007150154A5 - - Google Patents

Download PDF

Info

Publication number
JP2007150154A5
JP2007150154A5 JP2005345410A JP2005345410A JP2007150154A5 JP 2007150154 A5 JP2007150154 A5 JP 2007150154A5 JP 2005345410 A JP2005345410 A JP 2005345410A JP 2005345410 A JP2005345410 A JP 2005345410A JP 2007150154 A5 JP2007150154 A5 JP 2007150154A5
Authority
JP
Japan
Prior art keywords
semiconductor chip
wiring
disposed
semiconductor device
base substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005345410A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007150154A (ja
JP5016811B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2005345410A priority Critical patent/JP5016811B2/ja
Priority claimed from JP2005345410A external-priority patent/JP5016811B2/ja
Publication of JP2007150154A publication Critical patent/JP2007150154A/ja
Publication of JP2007150154A5 publication Critical patent/JP2007150154A5/ja
Application granted granted Critical
Publication of JP5016811B2 publication Critical patent/JP5016811B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2005345410A 2005-11-30 2005-11-30 半導体装置 Expired - Fee Related JP5016811B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005345410A JP5016811B2 (ja) 2005-11-30 2005-11-30 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005345410A JP5016811B2 (ja) 2005-11-30 2005-11-30 半導体装置

Publications (3)

Publication Number Publication Date
JP2007150154A JP2007150154A (ja) 2007-06-14
JP2007150154A5 true JP2007150154A5 (enExample) 2009-01-22
JP5016811B2 JP5016811B2 (ja) 2012-09-05

Family

ID=38211157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005345410A Expired - Fee Related JP5016811B2 (ja) 2005-11-30 2005-11-30 半導体装置

Country Status (1)

Country Link
JP (1) JP5016811B2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4571679B2 (ja) * 2008-01-18 2010-10-27 Okiセミコンダクタ株式会社 半導体装置
US8766440B2 (en) 2010-03-04 2014-07-01 Nec Corporation Wiring board with built-in semiconductor element
WO2011125380A1 (ja) 2010-04-08 2011-10-13 日本電気株式会社 半導体素子内蔵配線基板
KR101145041B1 (ko) * 2010-10-19 2012-05-11 주식회사 네패스 반도체칩 패키지, 반도체 모듈 및 그 제조 방법
KR102205195B1 (ko) * 2018-01-23 2021-01-20 주식회사 네패스 반도체 칩 적층 패키지 및 그 제조 방법
KR102061850B1 (ko) * 2018-02-26 2020-01-02 삼성전자주식회사 팬-아웃 반도체 패키지
US11171115B2 (en) 2019-03-18 2021-11-09 Kepler Computing Inc. Artificial intelligence processor with three-dimensional stacked memory
US11836102B1 (en) 2019-03-20 2023-12-05 Kepler Computing Inc. Low latency and high bandwidth artificial intelligence processor
KR102436025B1 (ko) * 2019-04-10 2022-08-25 주식회사 네패스 안테나를 포함하는 반도체 패키지
US12086410B1 (en) 2019-05-31 2024-09-10 Kepler Computing Inc. Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer
US11043472B1 (en) 2019-05-31 2021-06-22 Kepler Compute Inc. 3D integrated ultra high-bandwidth memory
US11844223B1 (en) 2019-05-31 2023-12-12 Kepler Computing Inc. Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
US11791233B1 (en) 2021-08-06 2023-10-17 Kepler Computing Inc. Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4157829B2 (ja) * 2003-06-03 2008-10-01 カシオ計算機株式会社 半導体装置およびその製造方法

Similar Documents

Publication Publication Date Title
TWI681519B (zh) 半導體裝置
JP5470510B2 (ja) 埋め込まれた導電性ポストを備える半導体パッケージ
TWI374536B (en) Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
US7598617B2 (en) Stack package utilizing through vias and re-distribution lines
JP2006093189A5 (enExample)
JP2007150154A5 (enExample)
TW200620577A (en) Package substrate for a semiconductor device, a fabrication method for same, and a semiconductor device
JP2010245455A5 (ja) 基板
TW200511534A (en) Tape circuit substrate and semiconductor chip package using the same
TW201316487A (zh) 積體電路封裝結構
JP2011044654A5 (enExample)
SG186536A1 (en) Integrated circuit packaging system with verticalinterconnects and method of manufacture thereof
JP2008078367A5 (enExample)
CN108447842A (zh) 一种指纹芯片的封装结构以及封装方法
CN104254190A (zh) 电路板及其制作方法
KR101078744B1 (ko) 적층 반도체 패키지
TWI701774B (zh) 半導體裝置
TWI269418B (en) Chip scale packaging with improved heat dissipation capability
CN102270584A (zh) 电路板结构、封装结构与制作电路板的方法
JP2007294488A5 (enExample)
TWI623251B (zh) 中介基板之製法
JP2007173606A5 (enExample)
TWI435667B (zh) 印刷電路板組件
JP3844079B2 (ja) 半導体装置の製造方法
TW201735318A (zh) 用於系統級封裝(sip)裝置的類似覆晶之整合式被動預封裝體