JP2007048974A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP2007048974A JP2007048974A JP2005232387A JP2005232387A JP2007048974A JP 2007048974 A JP2007048974 A JP 2007048974A JP 2005232387 A JP2005232387 A JP 2005232387A JP 2005232387 A JP2005232387 A JP 2005232387A JP 2007048974 A JP2007048974 A JP 2007048974A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- semiconductor device
- insulating film
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】半導体装置は、空洞15中に設けられCuを主成分とする配線層22−1と、前記配線層と電気的に接続されて所定の構成元素を含む層間絶縁膜17中に設けられCuを主成分とするビア層23−1とを備えた空中配線W1と、前記空中配線上に設けられたポーラス膜11−2と、前記空中配線の表面上を覆うように設けられ、前記所定の構成元素と所定の金属元素との化合物を主成分としたバリア膜(MnxSiyOz膜)25−1とを具備する。
【選択図】 図1
Description
以下、図1および図2を用いて、この発明の第1の実施形態に係る半導体装置を説明する。図1は、この実施形態に係る半導体装置を示す断面図である。
次に、図1および図2に示した半導体装置を例に挙げて、図3乃至図5を用いて説明する。尚、この説明においては、素子分離やMOSFET(Metal Oxide Semiconductor Field Effect Transistor)等の製造工程の図示は省略する。
次に、この発明の変形例1に係る半導体装置の製造方法について、図6、図7を用いて説明する。この変形例1に係る半導体装置の製造方法は、先にバリア膜を形成した後に、空洞を形成する場合に関する。この説明において、上記第1の実施形態と重複する部分の説明を省略する。
まず、半導体基板上に周知の製造方法を用いて、MOSFET等の素子構造を形成する。続いて、素子構造上を覆うように、例えば、CVD法を用いてSiOC等を堆積し、層間絶縁膜を形成する(図示せず)。
次に、この発明の第2の実施形態に係る半導体装置について、図8を用いて説明する。この実施形態に係る半導体装置は、配線層およびビア層が空洞中に設けられた場合に関する。この説明において、上記第1の実施形態と重複する部分の説明を省略する。
次に、この実施形態に係る半導体装置の製造方法について、図8に示した半導体装置を例に挙げて、図9乃至図11を用いて説明する。尚、この説明においては、素子分離やMOSFET等の製造工程の図示は省略する。
次に、この発明の変形例2に係る半導体装置の製造方法について、図12、図13を用いて説明する。この変形例2に係る半導体装置の製造方法は、先にバリア膜を形成した後に、空洞を形成する場合に関する。この説明において、上記第2の実施形態と重複する部分の説明を省略する。
まず、半導体基板上に周知の製造方法を用いて、MOSFET等の素子構造を形成する。続いて、素子構造上を覆うように、例えば、CVD法を用いてSiOC等を堆積し、層間絶縁膜を形成する(図示せず)。
次に、この発明の変形例3に係る半導体装置の製造方法について、図14乃至図16を用いて説明する。この説明において、上記第2の実施形態と重複する部分の説明を省略する。
まず、半導体基板上に周知の製造方法を用いて、MOSFET等の素子構造を形成する。続いて、素子構造上を覆うように、例えば、CVD法を用いてSiOC等を堆積し、層間絶縁膜を形成する(図示せず)。
Claims (5)
- 空洞中に設けられCuを主成分とする配線層と、前記配線層と電気的に接続されて所定の構成元素を含む層間絶縁膜中に設けられCuを主成分とするビア層とを備えた空中配線と、
前記空中配線上に設けられたポーラス膜と、
前記空中配線の表面上を覆うように設けられ、前記所定の構成元素と所定の金属元素との化合物を主成分としたバリア膜とを具備すること
を特徴とする半導体装置。 - 空洞中に設けられCuを主成分とする配線層と、前記配線層と電気的に接続されて前記空洞中に設けられCuを主成分とするビア層とを備えた空中配線と、
前記空中配線上に設けられたポーラス膜と、
前記空中配線の表面上を覆うように設けられ、所定の構成元素と所定の金属元素との化合物を主成分としたバリア膜とを具備すること
を特徴とする半導体装置。 - 前記層間絶縁膜上に設けられたエッチングストッパ膜を更に具備すること
を特徴とする請求項1に記載の半導体装置。 - 前記所定の金属元素は、Mn、Nb、Zr、Cr、V、Y、Tc、およびReからなる群から選択された少なくとも1つの元素を含み、
前記所定の構成元素は、Si、C、及びFからなる群から選択された少なくとも1つの元素とOとを含み、
前記バリア膜は、αxOy、αxSiyOz、αxCyOz、およびαxFyOzからなる群から選択された材料を主成分とし、ここで、αは前記所定の金属元素を表すこと
を特徴とする請求項1または2に記載の半導体装置。 - 少なくともSiを含む絶縁膜中に配線用の溝を形成する工程と、
前記溝中に、所定の金属元素を含みCuを主成分とする合金膜を埋め込む工程と、
前記合金膜上および前記絶縁膜上に、少なくともSiを含むポーラス膜を形成する工程と、
前記ポーラス膜越しに少なくともO2ガスを含んだエッチングを熱処理と共に行い、前記絶縁膜を除去して空洞を形成すると同時に、前記合金膜の表面上に前記所定の金属元素とSi元素と前記O2ガスからのO元素との化合物を主成分とするバリア膜を自己整合的に形成する工程とを具備すること
を特徴とする半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005232387A JP4197694B2 (ja) | 2005-08-10 | 2005-08-10 | 半導体装置およびその製造方法 |
US11/399,653 US7795733B2 (en) | 2005-08-10 | 2006-04-07 | Semiconductor device having aerial wiring and manufacturing method thereof |
US12/851,077 US20110027985A1 (en) | 2005-08-10 | 2010-08-05 | Semiconductor device having aerial wiring and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005232387A JP4197694B2 (ja) | 2005-08-10 | 2005-08-10 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007048974A true JP2007048974A (ja) | 2007-02-22 |
JP4197694B2 JP4197694B2 (ja) | 2008-12-17 |
Family
ID=37741865
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005232387A Expired - Fee Related JP4197694B2 (ja) | 2005-08-10 | 2005-08-10 | 半導体装置およびその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7795733B2 (ja) |
JP (1) | JP4197694B2 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007220738A (ja) * | 2006-02-14 | 2007-08-30 | Sony Corp | 半導体装置の製造方法 |
JP2009170872A (ja) * | 2007-10-09 | 2009-07-30 | Applied Materials Inc | 優勢エッチング抵抗性を具備する低k誘電バリアを得る方法 |
JP2010141024A (ja) * | 2008-12-10 | 2010-06-24 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
US8324730B2 (en) | 2008-12-19 | 2012-12-04 | Advanced Interconnect Materials Llc | Copper interconnection structure and method for forming copper interconnections |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4282646B2 (ja) * | 2005-09-09 | 2009-06-24 | 株式会社東芝 | 半導体装置の製造方法 |
WO2009001780A1 (ja) * | 2007-06-22 | 2008-12-31 | Rohm Co., Ltd. | 半導体装置およびその製造方法 |
JP5264187B2 (ja) * | 2008-01-08 | 2013-08-14 | パナソニック株式会社 | 半導体装置及びその製造方法 |
JP2009272563A (ja) * | 2008-05-09 | 2009-11-19 | Toshiba Corp | 半導体装置及びその製造方法 |
US8653663B2 (en) | 2009-10-29 | 2014-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer for copper interconnect |
US8456009B2 (en) | 2010-02-18 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having an air-gap region and a method of manufacturing the same |
US8421239B2 (en) * | 2010-03-16 | 2013-04-16 | International Business Machines Corporation | Crenulated wiring structure and method for integrated circuit interconnects |
US8896120B2 (en) * | 2010-04-27 | 2014-11-25 | International Business Machines Corporation | Structures and methods for air gap integration |
US8461683B2 (en) * | 2011-04-01 | 2013-06-11 | Intel Corporation | Self-forming, self-aligned barriers for back-end interconnects and methods of making same |
US8624394B2 (en) * | 2011-12-07 | 2014-01-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated technology for partial air gap low K deposition |
KR101898876B1 (ko) | 2012-03-02 | 2018-09-17 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US8722531B1 (en) * | 2012-11-01 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer for copper interconnect |
US9997457B2 (en) | 2013-12-20 | 2018-06-12 | Intel Corporation | Cobalt based interconnects and methods of fabrication thereof |
US9966339B2 (en) | 2014-03-14 | 2018-05-08 | Taiwan Semiconductor Manufacturing Company | Barrier structure for copper interconnect |
US9984975B2 (en) | 2014-03-14 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company | Barrier structure for copper interconnect |
KR102272553B1 (ko) * | 2015-01-19 | 2021-07-02 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
US9449874B1 (en) * | 2015-06-30 | 2016-09-20 | International Business Machines Corporation | Self-forming barrier for subtractive copper |
US9859156B2 (en) * | 2015-12-30 | 2018-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure with sidewall dielectric protection layer |
KR102616489B1 (ko) | 2016-10-11 | 2023-12-20 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3887035B2 (ja) * | 1995-12-28 | 2007-02-28 | 株式会社東芝 | 半導体装置の製造方法 |
US6054379A (en) * | 1998-02-11 | 2000-04-25 | Applied Materials, Inc. | Method of depositing a low k dielectric with organo silane |
US6448177B1 (en) * | 2001-03-27 | 2002-09-10 | Intle Corporation | Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure |
US6555467B2 (en) * | 2001-09-28 | 2003-04-29 | Sharp Laboratories Of America, Inc. | Method of making air gaps copper interconnect |
US6867125B2 (en) * | 2002-09-26 | 2005-03-15 | Intel Corporation | Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material |
US6924222B2 (en) * | 2002-11-21 | 2005-08-02 | Intel Corporation | Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide |
US7084479B2 (en) * | 2003-12-08 | 2006-08-01 | International Business Machines Corporation | Line level air gaps |
JP4478038B2 (ja) | 2004-02-27 | 2010-06-09 | 株式会社半導体理工学研究センター | 半導体装置及びその製造方法 |
-
2005
- 2005-08-10 JP JP2005232387A patent/JP4197694B2/ja not_active Expired - Fee Related
-
2006
- 2006-04-07 US US11/399,653 patent/US7795733B2/en not_active Expired - Fee Related
-
2010
- 2010-08-05 US US12/851,077 patent/US20110027985A1/en not_active Abandoned
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007220738A (ja) * | 2006-02-14 | 2007-08-30 | Sony Corp | 半導体装置の製造方法 |
JP2009170872A (ja) * | 2007-10-09 | 2009-07-30 | Applied Materials Inc | 優勢エッチング抵抗性を具備する低k誘電バリアを得る方法 |
JP2010141024A (ja) * | 2008-12-10 | 2010-06-24 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
US8324730B2 (en) | 2008-12-19 | 2012-12-04 | Advanced Interconnect Materials Llc | Copper interconnection structure and method for forming copper interconnections |
US8580688B2 (en) | 2008-12-19 | 2013-11-12 | Advanced Interconect Materials, LLC | Copper interconnection structure and method for forming copper interconnections |
Also Published As
Publication number | Publication date |
---|---|
US20110027985A1 (en) | 2011-02-03 |
US20070035032A1 (en) | 2007-02-15 |
US7795733B2 (en) | 2010-09-14 |
JP4197694B2 (ja) | 2008-12-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4197694B2 (ja) | 半導体装置およびその製造方法 | |
US9613900B2 (en) | Nanoscale interconnect structure | |
US7834457B2 (en) | Bilayer metal capping layer for interconnect applications | |
US8242600B2 (en) | Redundant metal barrier structure for interconnect applications | |
JP4741965B2 (ja) | 半導体装置およびその製造方法 | |
US8044519B2 (en) | Semiconductor device and method of fabricating the same | |
KR101072152B1 (ko) | 배리어 향상을 위한 산소/질소 전이 영역을 포함하는 도금시드층 | |
WO2009104233A1 (ja) | 半導体装置及びその製造方法 | |
JP2007173511A (ja) | 半導体装置の製造方法 | |
JP2008294040A (ja) | 半導体装置 | |
US20130149859A1 (en) | Tungsten metallization: structure and fabrication of same | |
US7482261B2 (en) | Interconnect structure for BEOL applications | |
US10930520B2 (en) | Self-formed liner for interconnect structures | |
JP5190415B2 (ja) | 半導体装置 | |
JP2008205177A (ja) | 半導体装置及びその製造方法 | |
JP2007220738A (ja) | 半導体装置の製造方法 | |
US7902076B2 (en) | Method of fabricating semiconductor device | |
JP4602091B2 (ja) | デュアルダマシン工程の中で銅の酸化防止方法 | |
JP2010080606A (ja) | 半導体装置の製造方法 | |
JP2004288763A (ja) | 半導体装置の製造方法及び半導体装置 | |
US9484252B2 (en) | Integrated circuits including selectively deposited metal capping layers on copper lines and methods for fabricating the same | |
JP2010073736A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080801 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080805 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080901 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080924 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080929 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111010 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111010 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111010 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121010 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131010 Year of fee payment: 5 |
|
LAPS | Cancellation because of no payment of annual fees |