JP2006518523A5 - - Google Patents

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Publication number
JP2006518523A5
JP2006518523A5 JP2004557464A JP2004557464A JP2006518523A5 JP 2006518523 A5 JP2006518523 A5 JP 2006518523A5 JP 2004557464 A JP2004557464 A JP 2004557464A JP 2004557464 A JP2004557464 A JP 2004557464A JP 2006518523 A5 JP2006518523 A5 JP 2006518523A5
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JP
Japan
Prior art keywords
memory
coupled
columns
column
memory array
Prior art date
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Pending
Application number
JP2004557464A
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English (en)
Japanese (ja)
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JP2006518523A (ja
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Publication date
Priority claimed from US10/309,572 external-priority patent/US6934208B2/en
Application filed filed Critical
Publication of JP2006518523A publication Critical patent/JP2006518523A/ja
Publication of JP2006518523A5 publication Critical patent/JP2006518523A5/ja
Pending legal-status Critical Current

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JP2004557464A 2002-12-03 2003-12-01 異なったメモリ・アレイのカラムにより共有される電流制限ブリーダ・デバイスのための装置および方法 Pending JP2006518523A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/309,572 US6934208B2 (en) 2002-12-03 2002-12-03 Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays
PCT/US2003/038226 WO2004051662A2 (en) 2002-12-03 2003-12-01 Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays

Publications (2)

Publication Number Publication Date
JP2006518523A JP2006518523A (ja) 2006-08-10
JP2006518523A5 true JP2006518523A5 (enExample) 2006-09-28

Family

ID=32392903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004557464A Pending JP2006518523A (ja) 2002-12-03 2003-12-01 異なったメモリ・アレイのカラムにより共有される電流制限ブリーダ・デバイスのための装置および方法

Country Status (8)

Country Link
US (1) US6934208B2 (enExample)
EP (1) EP1576347A2 (enExample)
JP (1) JP2006518523A (enExample)
KR (1) KR100788182B1 (enExample)
CN (1) CN101405809A (enExample)
AU (1) AU2003298793A1 (enExample)
TW (1) TWI285899B (enExample)
WO (1) WO2004051662A2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6934208B2 (en) 2002-12-03 2005-08-23 Boise Technology, Inc. Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays
KR100587080B1 (ko) * 2004-05-17 2006-06-08 주식회사 하이닉스반도체 메모리 장치의 감지 증폭기를 제어하여 컬럼성 페일을검출하는 방법 및 그 장치
US7698607B2 (en) * 2004-06-15 2010-04-13 Intel Corporation Repairing microdisplay frame buffers
US10020038B1 (en) 2017-04-14 2018-07-10 Micron Technology, Inc. Apparatuses and methods for controlling wordlines and sense amplifiers

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5235550A (en) * 1991-05-16 1993-08-10 Micron Technology, Inc. Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts
US5499211A (en) * 1995-03-13 1996-03-12 International Business Machines Corporation Bit-line precharge current limiter for CMOS dynamic memories
JP3782227B2 (ja) * 1997-03-11 2006-06-07 株式会社東芝 半導体記憶装置
US5896334A (en) * 1997-08-14 1999-04-20 Micron Technology, Inc. Circuit and method for memory device with defect current isolation
JP3505373B2 (ja) * 1997-11-14 2004-03-08 株式会社東芝 半導体記憶装置
JP2000077628A (ja) * 1998-06-19 2000-03-14 Toshiba Corp 半導体記憶装置
US6078538A (en) * 1998-08-20 2000-06-20 Micron Technology, Inc. Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts
JP2001052476A (ja) * 1999-08-05 2001-02-23 Mitsubishi Electric Corp 半導体装置
US6356492B1 (en) * 2000-08-16 2002-03-12 Micron Technology, Inc. Method and apparatus for reducing current drain caused by row to column shorts in a memory device
US6333882B1 (en) * 2000-08-25 2001-12-25 Micron Technology, Inc. Equilibration/pre-charge circuit for a memory device
US6678199B1 (en) * 2002-06-19 2004-01-13 Micron Technology, Inc. Memory device with sense amp equilibration circuit
US6934208B2 (en) 2002-12-03 2005-08-23 Boise Technology, Inc. Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays

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