KR100788182B1 - 상이한 메모리 어레이들의 열들에 의해 공유되는 전류 제한 블리더 장치를 위한 장치 및 방법 - Google Patents

상이한 메모리 어레이들의 열들에 의해 공유되는 전류 제한 블리더 장치를 위한 장치 및 방법 Download PDF

Info

Publication number
KR100788182B1
KR100788182B1 KR1020057010141A KR20057010141A KR100788182B1 KR 100788182 B1 KR100788182 B1 KR 100788182B1 KR 1020057010141 A KR1020057010141 A KR 1020057010141A KR 20057010141 A KR20057010141 A KR 20057010141A KR 100788182 B1 KR100788182 B1 KR 100788182B1
Authority
KR
South Korea
Prior art keywords
memory
coupled
columns
bleeder
column
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020057010141A
Other languages
English (en)
Korean (ko)
Other versions
KR20050084162A (ko
Inventor
제이. 웨인 톰슨
조지 비. 라드
하워드 씨. 커시
Original Assignee
마이크론 테크놀로지 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 마이크론 테크놀로지 인코포레이티드 filed Critical 마이크론 테크놀로지 인코포레이티드
Publication of KR20050084162A publication Critical patent/KR20050084162A/ko
Application granted granted Critical
Publication of KR100788182B1 publication Critical patent/KR100788182B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
KR1020057010141A 2002-12-03 2003-12-01 상이한 메모리 어레이들의 열들에 의해 공유되는 전류 제한 블리더 장치를 위한 장치 및 방법 Expired - Fee Related KR100788182B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/309,572 US6934208B2 (en) 2002-12-03 2002-12-03 Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays
US10/309,572 2002-12-03

Publications (2)

Publication Number Publication Date
KR20050084162A KR20050084162A (ko) 2005-08-26
KR100788182B1 true KR100788182B1 (ko) 2008-01-02

Family

ID=32392903

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020057010141A Expired - Fee Related KR100788182B1 (ko) 2002-12-03 2003-12-01 상이한 메모리 어레이들의 열들에 의해 공유되는 전류 제한 블리더 장치를 위한 장치 및 방법

Country Status (8)

Country Link
US (1) US6934208B2 (enExample)
EP (1) EP1576347A2 (enExample)
JP (1) JP2006518523A (enExample)
KR (1) KR100788182B1 (enExample)
CN (1) CN101405809A (enExample)
AU (1) AU2003298793A1 (enExample)
TW (1) TWI285899B (enExample)
WO (1) WO2004051662A2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6934208B2 (en) 2002-12-03 2005-08-23 Boise Technology, Inc. Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays
KR100587080B1 (ko) * 2004-05-17 2006-06-08 주식회사 하이닉스반도체 메모리 장치의 감지 증폭기를 제어하여 컬럼성 페일을검출하는 방법 및 그 장치
US7698607B2 (en) * 2004-06-15 2010-04-13 Intel Corporation Repairing microdisplay frame buffers
US10020038B1 (en) 2017-04-14 2018-07-10 Micron Technology, Inc. Apparatuses and methods for controlling wordlines and sense amplifiers

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5499211A (en) 1995-03-13 1996-03-12 International Business Machines Corporation Bit-line precharge current limiter for CMOS dynamic memories
US6144599A (en) 1997-11-14 2000-11-07 Kabushiki Kaisha Toshiba Semiconductor memory device
US6181618B1 (en) 1997-03-11 2001-01-30 Kabushiki Kaisha Toshiba Dynamic type RAM

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5235550A (en) * 1991-05-16 1993-08-10 Micron Technology, Inc. Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts
US5896334A (en) * 1997-08-14 1999-04-20 Micron Technology, Inc. Circuit and method for memory device with defect current isolation
JP2000077628A (ja) * 1998-06-19 2000-03-14 Toshiba Corp 半導体記憶装置
US6078538A (en) * 1998-08-20 2000-06-20 Micron Technology, Inc. Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts
JP2001052476A (ja) * 1999-08-05 2001-02-23 Mitsubishi Electric Corp 半導体装置
US6356492B1 (en) * 2000-08-16 2002-03-12 Micron Technology, Inc. Method and apparatus for reducing current drain caused by row to column shorts in a memory device
US6333882B1 (en) * 2000-08-25 2001-12-25 Micron Technology, Inc. Equilibration/pre-charge circuit for a memory device
US6678199B1 (en) * 2002-06-19 2004-01-13 Micron Technology, Inc. Memory device with sense amp equilibration circuit
US6934208B2 (en) 2002-12-03 2005-08-23 Boise Technology, Inc. Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5499211A (en) 1995-03-13 1996-03-12 International Business Machines Corporation Bit-line precharge current limiter for CMOS dynamic memories
US6181618B1 (en) 1997-03-11 2001-01-30 Kabushiki Kaisha Toshiba Dynamic type RAM
US6144599A (en) 1997-11-14 2000-11-07 Kabushiki Kaisha Toshiba Semiconductor memory device

Also Published As

Publication number Publication date
US6934208B2 (en) 2005-08-23
TW200428403A (en) 2004-12-16
AU2003298793A1 (en) 2004-06-23
US20040105333A1 (en) 2004-06-03
WO2004051662A2 (en) 2004-06-17
CN101405809A (zh) 2009-04-08
EP1576347A2 (en) 2005-09-21
KR20050084162A (ko) 2005-08-26
TWI285899B (en) 2007-08-21
JP2006518523A (ja) 2006-08-10

Similar Documents

Publication Publication Date Title
KR100304506B1 (ko) 어레이에지기준감지동작을수행하는dram
US10347321B1 (en) Apparatuses and methods for providing driving signals in semiconductor devices
US5715189A (en) Semiconductor memory device having hierarchical bit line arrangement
US5808955A (en) Integrated circuit memory devices including sub-word line drivers and related methods
US5699289A (en) Power source circuit and wiring group for semiconductor memory device
US7684272B2 (en) Semiconductor memory device with transfer switch and method of operating the device
US5323349A (en) Dynamic semiconductor memory device having separate read and write data bases
US5959898A (en) Dynamic cell plate sensing and equilibration in a memory device
US5694368A (en) Memory device with efficient redundancy using sense amplifiers
US5625599A (en) Semiconductor memory having decoded sense amplifier drive lines
US5926410A (en) Memory array architecture and method for dynamic cell plate sensing
US6717867B2 (en) SRAM power-up system and method
KR100788182B1 (ko) 상이한 메모리 어레이들의 열들에 의해 공유되는 전류 제한 블리더 장치를 위한 장치 및 방법
US6590819B1 (en) Digit line equilibration using time-multiplexed isolation
KR100284467B1 (ko) Dram센싱을위한셀플레이트기준화
US6504777B1 (en) Enhanced bitline equalization for hierarchical bitline architecture
US6356474B1 (en) Efficient open-array memory device architecture and method
US5973975A (en) Method and circuit for sharing sense amplifier drivers
US20070223302A1 (en) Reducing leakage current in memory device using bitline isolation
US6838337B2 (en) Sense amplifier and architecture for open digit arrays
EP0169460A2 (en) Dynamic memory array with segmented and quasi-folded bit lines
KR0164793B1 (ko) 반도체 메모리장치의 메모리셀 어레이 블럭 활성화 제어방법 및 그 회로
KR20040010521A (ko) 메모리 셀들의 결함있는 열들을 수리하는 방법 및 장치

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20111122

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20121119

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20131218

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20131218

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000