JP2006508548A - ドープされたｈｉｇｈ−ｋサイドウォールスペーサを有す電界効果トランジスタのドレイン／ソース拡張構造 - Google Patents

ドープされたｈｉｇｈ−ｋサイドウォールスペーサを有す電界効果トランジスタのドレイン／ソース拡張構造 Download PDF

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JP2006508548A
JP2006508548A JP2004570755A JP2004570755A JP2006508548A JP 2006508548 A JP2006508548 A JP 2006508548A JP 2004570755 A JP2004570755 A JP 2004570755A JP 2004570755 A JP2004570755 A JP 2004570755A JP 2006508548 A JP2006508548 A JP 2006508548A
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Prior art keywords
dielectric layer
dopant
region
substrate
layer
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JP2004570755A
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Japanese (ja)
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JP2006508548A5 (cg-RX-API-DMAC10.html
Inventor
フォイデル トーマス
ホルストマン マンフレッド
ビークツォレク カルシュテン
クリューゲル シュテファン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Priority claimed from DE10255849A external-priority patent/DE10255849B4/de
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2006508548A publication Critical patent/JP2006508548A/ja
Publication of JP2006508548A5 publication Critical patent/JP2006508548A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1404—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase
    • H10P32/1406—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
JP2004570755A 2002-11-29 2003-11-06 ドープされたｈｉｇｈ−ｋサイドウォールスペーサを有す電界効果トランジスタのドレイン／ソース拡張構造 Pending JP2006508548A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10255849A DE10255849B4 (de) 2002-11-29 2002-11-29 Verbesserte Drain/Source-Erweiterungsstruktur eines Feldeffekttransistors mit dotierten Seitenwandabstandselementen mit hoher Permittivität und Verfahren zu deren Herstellung
US10/442,745 US6849516B2 (en) 2002-11-29 2003-05-21 Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer
PCT/US2003/035355 WO2004051728A1 (en) 2002-11-29 2003-11-06 Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers

Publications (2)

Publication Number Publication Date
JP2006508548A true JP2006508548A (ja) 2006-03-09
JP2006508548A5 JP2006508548A5 (cg-RX-API-DMAC10.html) 2006-12-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004570755A Pending JP2006508548A (ja) 2002-11-29 2003-11-06 ドープされたｈｉｇｈ−ｋサイドウォールスペーサを有す電界効果トランジスタのドレイン／ソース拡張構造

Country Status (6)

Country Link
US (1) US20050098818A1 (cg-RX-API-DMAC10.html)
EP (1) EP1565934A1 (cg-RX-API-DMAC10.html)
JP (1) JP2006508548A (cg-RX-API-DMAC10.html)
KR (1) KR101022854B1 (cg-RX-API-DMAC10.html)
AU (1) AU2003295406A1 (cg-RX-API-DMAC10.html)
WO (1) WO2004051728A1 (cg-RX-API-DMAC10.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013016782A (ja) * 2011-06-10 2013-01-24 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
WO2016059754A1 (ja) * 2014-10-16 2016-04-21 国立研究開発法人科学技術振興機構 電界効果トランジスタ

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* Cited by examiner, † Cited by third party
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DE10324657B4 (de) * 2003-05-30 2009-01-22 Advanced Micro Devices, Inc. (n.d.Ges.d. Staates Delaware), Sunnyvale Verfahren zur Herstellung eines Metallsilizids
US8022465B2 (en) * 2005-11-15 2011-09-20 Macronrix International Co., Ltd. Low hydrogen concentration charge-trapping layer structures for non-volatile memory
EP1890322A3 (en) * 2006-08-15 2012-02-15 Kovio, Inc. Printed dopant layers
US8106455B2 (en) * 2009-04-30 2012-01-31 International Business Machines Corporation Threshold voltage adjustment through gate dielectric stack modification
KR101205037B1 (ko) 2011-02-28 2012-11-26 에스케이하이닉스 주식회사 반도체 소자 및 그 형성방법
US8673731B2 (en) * 2012-08-20 2014-03-18 International Business Machines Corporation Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices
GB2521457A (en) * 2013-12-20 2015-06-24 Isis Innovation Charge stabilized dielectric film for electronic devices
KR102300071B1 (ko) * 2020-02-12 2021-09-07 포항공과대학교 산학협력단 고 유전율 필드 플레이트를 구비한 드레인 확장형 핀펫 및 이의 제조방법

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JPS61191025A (ja) * 1985-02-20 1986-08-25 Fujitsu Ltd 半導体装置の製造方法
JPH04320036A (ja) * 1991-04-18 1992-11-10 Hitachi Ltd 半導体装置およびその製造方法
JPH05190845A (ja) * 1992-07-23 1993-07-30 Hitachi Ltd Ｍｉｓ型電界効果トランジスタ
JPH05343418A (ja) * 1992-06-09 1993-12-24 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPH07130998A (ja) * 1993-11-01 1995-05-19 Nec Corp 半導体装置の製造方法

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US4994869A (en) * 1989-06-30 1991-02-19 Texas Instruments Incorporated NMOS transistor having inversion layer source/drain contacts
EP0550255B1 (en) * 1991-12-31 1998-03-11 STMicroelectronics, Inc. Transistor spacer structure
US5814869A (en) * 1992-01-28 1998-09-29 Thunderbird Technologies, Inc. Short channel fermi-threshold field effect transistors
KR970006262B1 (ko) * 1994-02-04 1997-04-25 금성일렉트론 주식회사 도우핑된 디스포저블층(disposable layer)을 이용한 모스트랜지스터의 제조방법
US5518945A (en) * 1995-05-05 1996-05-21 International Business Machines Corporation Method of making a diffused lightly doped drain device with built in etch stop
US5770490A (en) * 1996-08-29 1998-06-23 International Business Machines Corporation Method for producing dual work function CMOS device
US5926715A (en) * 1997-06-04 1999-07-20 Mosel Vitelic Inc. Method of forming lightly-doped drain by automatic PSG doping
US6333556B1 (en) * 1997-10-09 2001-12-25 Micron Technology, Inc. Insulating materials
US6271563B1 (en) * 1998-07-27 2001-08-07 Advanced Micro Devices, Inc. MOS transistor with high-K spacer designed for ultra-large-scale integration
US6200869B1 (en) * 1998-11-06 2001-03-13 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit with ultra-shallow source/drain extensions
US6630712B2 (en) * 1999-08-11 2003-10-07 Advanced Micro Devices, Inc. Transistor with dynamic source/drain extensions
US6093590A (en) * 1999-09-14 2000-07-25 Worldwide Semiconductor Manufacturing Corp. Method of fabricating transistor having a metal gate and a gate dielectric layer with a high dielectric constant
US6255152B1 (en) * 1999-10-01 2001-07-03 United Microelectronics Corp. Method of fabricating CMOS using Si-B layer to form source/drain extension junction
US6417046B1 (en) * 2000-05-05 2002-07-09 Taiwan Semiconductor Manufacturing Company Modified nitride spacer for solving charge retention issue in floating gate memory cell
KR100439345B1 (ko) * 2000-10-31 2004-07-07 피티플러스(주) 폴리실리콘 활성층을 포함하는 박막트랜지스터 및 제조 방법
KR100397370B1 (ko) * 2001-10-29 2003-09-13 한국전자통신연구원 얕은 접합을 갖는 집적회로의 제조 방법

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JPS61191025A (ja) * 1985-02-20 1986-08-25 Fujitsu Ltd 半導体装置の製造方法
JPH04320036A (ja) * 1991-04-18 1992-11-10 Hitachi Ltd 半導体装置およびその製造方法
JPH05343418A (ja) * 1992-06-09 1993-12-24 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPH05190845A (ja) * 1992-07-23 1993-07-30 Hitachi Ltd Ｍｉｓ型電界効果トランジスタ
JPH07130998A (ja) * 1993-11-01 1995-05-19 Nec Corp 半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013016782A (ja) * 2011-06-10 2013-01-24 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US9837545B2 (en) 2011-06-10 2017-12-05 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US10833202B2 (en) 2011-06-10 2020-11-10 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
WO2016059754A1 (ja) * 2014-10-16 2016-04-21 国立研究開発法人科学技術振興機構 電界効果トランジスタ

Also Published As

Publication number Publication date
KR20050084030A (ko) 2005-08-26
WO2004051728A1 (en) 2004-06-17
AU2003295406A1 (en) 2004-06-23
EP1565934A1 (en) 2005-08-24
KR101022854B1 (ko) 2011-03-17
US20050098818A1 (en) 2005-05-12

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