JP2006501669A - 半導体材料のウエハのための高速アニーリングプロセス - Google Patents
半導体材料のウエハのための高速アニーリングプロセス Download PDFInfo
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- JP2006501669A JP2006501669A JP2004541118A JP2004541118A JP2006501669A JP 2006501669 A JP2006501669 A JP 2006501669A JP 2004541118 A JP2004541118 A JP 2004541118A JP 2004541118 A JP2004541118 A JP 2004541118A JP 2006501669 A JP2006501669 A JP 2006501669A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000000137 annealing Methods 0.000 title claims abstract description 22
- 239000000463 material Substances 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 235000012431 wafers Nutrition 0.000 title description 47
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 238000004381 surface treatment Methods 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000000630 rising effect Effects 0.000 abstract 1
- 230000006641 stabilisation Effects 0.000 abstract 1
- 238000011105 stabilization Methods 0.000 abstract 1
- 238000004151 rapid thermal annealing Methods 0.000 description 27
- 230000007704 transition Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
・加熱の開始を意図した温度上昇の第1の勾配と、
・温度の安定を意図した第1の安定停止状態と、
・温度上昇の第2の勾配と
を連続的に含む高速アニーリング段階を有するプロセスに関する。
・ウエハが約750℃の値までの温度となる第1の勾配 − その後に、この温度で約10秒間停止状態となる。この第1の勾配およびそれに続く停止状態により、
>加熱が開始され、
>RTAに晒されるウエハの温度の確認を開始でき(この確認は、ウエハの温度を決定するパイロメータによって行なわれるが、ウエハは、ウエハの材料に依存する特定の温度(シリコンウエハの場合、この温度は約400℃)のみでしかパイロメータによって読み取ることができない)、
>温度を安定させることができる(これは、特に停止状態の役割である)。
・加熱の開始を意図した温度上昇の第1の勾配と、
・温度の安定を意図した第1の安定停止状態と、
・温度上昇の第2の勾配と
を連続的に含む高速アニーリング段階を有するプロセスにおいて、
前記第2の勾配中、温度上昇の平均的な傾きは、ローとして知られる第1の低温範囲内の第1の値を有し、その後にハイとして知られる高温範囲内で上昇することを特徴とするプロセスを提案する。
・前記ウエハがシリコンからなるウエハであり、
・前記ウエハがSOIウエハであり、
・前記第1の停止状態が約750℃の温度で起こり、
・前記低温範囲が約800〜約1100℃にわたり、
・前記高温範囲内で温度が連続的に上昇し、
・前記低温範囲内で温度が中間停止状態をもって上昇し、
・前記高速アニーリング段階は、約1150〜1250℃の温度の停止状態で終了し、
・前記第2の勾配が約25〜50℃/秒の傾きで終了する。
低温範囲で要する時間(秒) 観察されたスリップラインの平均数
7 46.5
14.5 30
19 14
26 6.5
Claims (9)
- 半導体材料の中から選択された材料で形成されたウエハの表面処理プロセスであって、前記ウエハが転移技術によって得られ、
・加熱の開始を意図した温度上昇の第1の勾配と、
・温度の安定を意図した第1の安定停止状態と、
・温度上昇の第2の勾配と
を連続的に含む高速アニーリング段階を有するプロセスにおいて、
前記第2の勾配中、温度上昇の平均的な傾きは、ローとして知られる第1の低温範囲内の第1の値を有し、その後にハイとして知られる高温範囲内で上昇する
ことを特徴とするプロセス。 - 前記ウエハがシリコンからなるウエハであることを特徴とする、先行する請求項に記載のプロセス。
- 前記ウエハがSOIウエハであることを特徴とする、先行する請求項に記載のプロセス。
- 前記第1の停止状態が約750℃の温度で起こることを特徴とする、先行する2つの請求項の何れかに記載のプロセス。
- 前記低温範囲が約800〜約1100℃にわたることを特徴とする、先行する3つの請求項の何れかに記載のプロセス。
- 前記低温範囲内で温度が連続的に上昇することを特徴とする、先行する請求項の何れかに記載のプロセス。
- 前記低温範囲内で温度が中間停止状態をもって上昇することを特徴とする、請求項1ないし5の何れかに記載のプロセス。
- 前記高速アニーリング段階は、約1150〜1250℃の温度の停止状態で終了することを特徴とする、先行する請求項の何れかに記載のプロセス。
- 前記第2の勾配が約25〜50℃/秒の傾きで終了することを特徴とする、先行する請求項の何れかに記載のプロセス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0212120A FR2845202B1 (fr) | 2002-10-01 | 2002-10-01 | Procede de recuit rapide de tranches de materiau semiconducteur. |
PCT/IB2003/004590 WO2004032227A1 (en) | 2002-10-01 | 2003-09-26 | Rapid annealing process for wafers in semiconductor material |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006501669A true JP2006501669A (ja) | 2006-01-12 |
JP2006501669A5 JP2006501669A5 (ja) | 2006-04-27 |
Family
ID=31985363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004541118A Pending JP2006501669A (ja) | 2002-10-01 | 2003-09-26 | 半導体材料のウエハのための高速アニーリングプロセス |
Country Status (9)
Country | Link |
---|---|
US (1) | US7138344B2 (ja) |
EP (1) | EP1552553A1 (ja) |
JP (1) | JP2006501669A (ja) |
KR (1) | KR100758053B1 (ja) |
CN (1) | CN100336196C (ja) |
AU (1) | AU2003267793A1 (ja) |
FR (1) | FR2845202B1 (ja) |
TW (1) | TWI278936B (ja) |
WO (1) | WO2004032227A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008023701A1 (fr) * | 2006-08-25 | 2008-02-28 | Sumco Techxiv Corporation | Procédé de traitement thermique d'une plaquette de silicium |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100818842B1 (ko) * | 2006-12-27 | 2008-04-01 | 주식회사 실트론 | 웨이퍼의 열처리시 슬립을 방지할 수 있는 웨이퍼 지지 핀및 웨이퍼의 열처리 방법 |
FR2938119B1 (fr) | 2008-10-30 | 2011-04-22 | Soitec Silicon On Insulator | Procede de detachement de couches semi-conductrices a basse temperature |
FR2941324B1 (fr) * | 2009-01-22 | 2011-04-29 | Soitec Silicon On Insulator | Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant. |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07321120A (ja) * | 1994-05-25 | 1995-12-08 | Komatsu Electron Metals Co Ltd | シリコンウェーハの熱処理方法 |
JPH08250688A (ja) * | 1995-03-13 | 1996-09-27 | Mitsubishi Materials Corp | Soi基板及びその製造方法 |
JPH11168106A (ja) * | 1997-09-30 | 1999-06-22 | Fujitsu Ltd | 半導体基板の処理方法 |
JP2000091342A (ja) * | 1998-09-14 | 2000-03-31 | Shin Etsu Handotai Co Ltd | シリコンウエーハの熱処理方法及びシリコンウエーハ |
WO2001015215A1 (fr) * | 1999-08-20 | 2001-03-01 | S.O.I.Tec Silicon On Insulator Technologies | Procede de traitement de substrats pour la micro-electronique et substrats obtenus par ce procede |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0119374B1 (fr) * | 1983-03-18 | 1987-09-02 | ATELIERS DE CONSTRUCTIONS ELECTRIQUES DE CHARLEROI (ACEC) Société Anonyme | Procédé pour le contrôle de la marche d'une machine électrique et dispositif appliquant ce procédé |
US5359693A (en) * | 1991-07-15 | 1994-10-25 | Ast Elektronik Gmbh | Method and apparatus for a rapid thermal processing of delicate components |
JPH1012626A (ja) * | 1996-06-26 | 1998-01-16 | Sony Corp | 半導体装置の製造方法 |
JP3450163B2 (ja) | 1997-09-12 | 2003-09-22 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
FR2777115B1 (fr) * | 1998-04-07 | 2001-07-13 | Commissariat Energie Atomique | Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede |
JP2002110688A (ja) * | 2000-09-29 | 2002-04-12 | Canon Inc | Soiの熱処理方法及び製造方法 |
-
2002
- 2002-10-01 FR FR0212120A patent/FR2845202B1/fr not_active Expired - Fee Related
-
2003
- 2003-09-25 US US10/671,813 patent/US7138344B2/en not_active Expired - Fee Related
- 2003-09-26 AU AU2003267793A patent/AU2003267793A1/en not_active Abandoned
- 2003-09-26 WO PCT/IB2003/004590 patent/WO2004032227A1/en active Application Filing
- 2003-09-26 CN CNB038235196A patent/CN100336196C/zh not_active Expired - Fee Related
- 2003-09-26 JP JP2004541118A patent/JP2006501669A/ja active Pending
- 2003-09-26 KR KR1020057005735A patent/KR100758053B1/ko not_active IP Right Cessation
- 2003-09-26 EP EP03748489A patent/EP1552553A1/en not_active Withdrawn
- 2003-09-30 TW TW092126922A patent/TWI278936B/zh not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07321120A (ja) * | 1994-05-25 | 1995-12-08 | Komatsu Electron Metals Co Ltd | シリコンウェーハの熱処理方法 |
JPH08250688A (ja) * | 1995-03-13 | 1996-09-27 | Mitsubishi Materials Corp | Soi基板及びその製造方法 |
JPH11168106A (ja) * | 1997-09-30 | 1999-06-22 | Fujitsu Ltd | 半導体基板の処理方法 |
JP2000091342A (ja) * | 1998-09-14 | 2000-03-31 | Shin Etsu Handotai Co Ltd | シリコンウエーハの熱処理方法及びシリコンウエーハ |
WO2001015215A1 (fr) * | 1999-08-20 | 2001-03-01 | S.O.I.Tec Silicon On Insulator Technologies | Procede de traitement de substrats pour la micro-electronique et substrats obtenus par ce procede |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008023701A1 (fr) * | 2006-08-25 | 2008-02-28 | Sumco Techxiv Corporation | Procédé de traitement thermique d'une plaquette de silicium |
Also Published As
Publication number | Publication date |
---|---|
EP1552553A1 (en) | 2005-07-13 |
US7138344B2 (en) | 2006-11-21 |
WO2004032227A1 (en) | 2004-04-15 |
US20040106303A1 (en) | 2004-06-03 |
CN1685497A (zh) | 2005-10-19 |
KR20050048669A (ko) | 2005-05-24 |
KR100758053B1 (ko) | 2007-09-11 |
FR2845202A1 (fr) | 2004-04-02 |
TWI278936B (en) | 2007-04-11 |
CN100336196C (zh) | 2007-09-05 |
FR2845202B1 (fr) | 2004-11-05 |
AU2003267793A1 (en) | 2004-04-23 |
TW200416894A (en) | 2004-09-01 |
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