JP2006344929A - 強誘電体キャパシタの製造方法及びこれを利用した半導体装置の製造方法 - Google Patents

強誘電体キャパシタの製造方法及びこれを利用した半導体装置の製造方法 Download PDF

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Publication number
JP2006344929A
JP2006344929A JP2006092049A JP2006092049A JP2006344929A JP 2006344929 A JP2006344929 A JP 2006344929A JP 2006092049 A JP2006092049 A JP 2006092049A JP 2006092049 A JP2006092049 A JP 2006092049A JP 2006344929 A JP2006344929 A JP 2006344929A
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JP
Japan
Prior art keywords
layer
hard mask
lower electrode
forming
ferroelectric
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006092049A
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English (en)
Japanese (ja)
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JP2006344929A5 (enExample
Inventor
Hwa-Young Ko
化永 高
Suk-Ho Joo
石昊 朱
丙才 ▲ペ▼
Byoung Jae Bae
Heui-Seog Kim
金　熙錫
Kyung-Rae Byun
▲キュン▼來 邊
Jin-Hwan Ham
陳煥 咸
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2006344929A publication Critical patent/JP2006344929A/ja
Publication of JP2006344929A5 publication Critical patent/JP2006344929A5/ja
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/694—Electrodes comprising noble metals or noble metal oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
JP2006092049A 2005-06-07 2006-03-29 強誘電体キャパシタの製造方法及びこれを利用した半導体装置の製造方法 Withdrawn JP2006344929A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050048531A KR100725451B1 (ko) 2005-06-07 2005-06-07 강유전체 캐패시터의 제조 방법 및 이를 이용한 반도체장치의 제조 방법

Publications (2)

Publication Number Publication Date
JP2006344929A true JP2006344929A (ja) 2006-12-21
JP2006344929A5 JP2006344929A5 (enExample) 2009-04-16

Family

ID=37493308

Family Applications (1)

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JP2006092049A Withdrawn JP2006344929A (ja) 2005-06-07 2006-03-29 強誘電体キャパシタの製造方法及びこれを利用した半導体装置の製造方法

Country Status (3)

Country Link
US (1) US20060273366A1 (enExample)
JP (1) JP2006344929A (enExample)
KR (1) KR100725451B1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
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JP2021534575A (ja) * 2018-08-10 2021-12-09 東京エレクトロン株式会社 ルテニウムハードマスクプロセス

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KR100456829B1 (ko) * 2002-06-17 2004-11-10 삼성전자주식회사 듀얼다마신공정에 적합한 엠아이엠 캐패시터 및 그의제조방법
JP4596167B2 (ja) * 2006-02-24 2010-12-08 セイコーエプソン株式会社 キャパシタの製造方法
JP5028829B2 (ja) * 2006-03-09 2012-09-19 セイコーエプソン株式会社 強誘電体メモリ装置の製造方法
KR100763559B1 (ko) * 2006-07-18 2007-10-04 삼성전자주식회사 강유전체막의 형성 방법 및 이를 이용한 강유전체캐패시터의 제조 방법
US7582549B2 (en) 2006-08-25 2009-09-01 Micron Technology, Inc. Atomic layer deposited barium strontium titanium oxide films
US7833914B2 (en) * 2007-04-27 2010-11-16 Micron Technology, Inc. Capacitors and methods with praseodymium oxide insulators
US8154850B2 (en) * 2007-05-11 2012-04-10 Paratek Microwave, Inc. Systems and methods for a thin film capacitor having a composite high-k thin film stack
US10115527B2 (en) 2015-03-09 2018-10-30 Blackberry Limited Thin film dielectric stack
US10297658B2 (en) 2016-06-16 2019-05-21 Blackberry Limited Method and apparatus for a thin film dielectric stack
US10950444B2 (en) * 2018-01-30 2021-03-16 Tokyo Electron Limited Metal hard mask layers for processing of microelectronic workpieces
JP7066585B2 (ja) * 2018-09-19 2022-05-13 キオクシア株式会社 記憶装置
JP7310146B2 (ja) * 2019-01-16 2023-07-19 東京エレクトロン株式会社 ハードマスク付き半導体デバイスの製造用の基板及び半導体デバイスの製造方法
US20200286685A1 (en) * 2019-03-06 2020-09-10 Intel Corporation Capacitor with epitaxial strain engineering
US11532439B2 (en) * 2019-03-07 2022-12-20 Intel Corporation Ultra-dense ferroelectric memory with self-aligned patterning
US20220415651A1 (en) * 2021-06-29 2022-12-29 Applied Materials, Inc. Methods Of Forming Memory Device With Reduced Resistivity

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000040800A (ja) * 1998-07-24 2000-02-08 Sharp Corp 強誘電体記憶素子及びその製造方法
US6674633B2 (en) * 2001-02-28 2004-01-06 Fujitsu Limited Process for producing a strontium ruthenium oxide protective layer on a top electrode
US6495413B2 (en) * 2001-02-28 2002-12-17 Ramtron International Corporation Structure for masking integrated capacitors of particular utility for ferroelectric memory integrated circuits
KR20030002095A (ko) * 2001-06-30 2003-01-08 주식회사 하이닉스반도체 강유전체 메모리 소자의 캐패시터 제조 방법
JP4014902B2 (ja) * 2002-03-15 2007-11-28 富士通株式会社 半導体装置の製造方法
KR100875647B1 (ko) * 2002-05-17 2008-12-24 주식회사 하이닉스반도체 반도체소자의 캐패시터 형성방법
KR100454255B1 (ko) * 2002-12-30 2004-10-26 주식회사 하이닉스반도체 하드마스크를 이용한 캐패시터의 제조 방법
US7250349B2 (en) * 2003-03-06 2007-07-31 Texas Instruments Incorporated Method for forming ferroelectric memory capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021534575A (ja) * 2018-08-10 2021-12-09 東京エレクトロン株式会社 ルテニウムハードマスクプロセス
JP7357846B2 (ja) 2018-08-10 2023-10-10 東京エレクトロン株式会社 ルテニウムハードマスクプロセス

Also Published As

Publication number Publication date
US20060273366A1 (en) 2006-12-07
KR20060127507A (ko) 2006-12-13
KR100725451B1 (ko) 2007-06-07

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