JP2006319326A5 - - Google Patents

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Publication number
JP2006319326A5
JP2006319326A5 JP2006114623A JP2006114623A JP2006319326A5 JP 2006319326 A5 JP2006319326 A5 JP 2006319326A5 JP 2006114623 A JP2006114623 A JP 2006114623A JP 2006114623 A JP2006114623 A JP 2006114623A JP 2006319326 A5 JP2006319326 A5 JP 2006319326A5
Authority
JP
Japan
Prior art keywords
doping
forming
silicon substrate
gate
recessed portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2006114623A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006319326A (ja
Filing date
Publication date
Priority claimed from US11/107,843 external-priority patent/US7605042B2/en
Application filed filed Critical
Publication of JP2006319326A publication Critical patent/JP2006319326A/ja
Publication of JP2006319326A5 publication Critical patent/JP2006319326A5/ja
Abandoned legal-status Critical Current

Links

JP2006114623A 2005-04-18 2006-04-18 ポリの高さ低減のためのＳＯＩ底プレドーピングを合併したｅ−ＳｉＧｅ Abandoned JP2006319326A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/107,843 US7605042B2 (en) 2005-04-18 2005-04-18 SOI bottom pre-doping merged e-SiGe for poly height reduction

Publications (2)

Publication Number Publication Date
JP2006319326A JP2006319326A (ja) 2006-11-24
JP2006319326A5 true JP2006319326A5 (enExample) 2007-11-29

Family

ID=37109033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006114623A Abandoned JP2006319326A (ja) 2005-04-18 2006-04-18 ポリの高さ低減のためのＳＯＩ底プレドーピングを合併したｅ−ＳｉＧｅ

Country Status (4)

Country Link
US (1) US7605042B2 (enExample)
JP (1) JP2006319326A (enExample)
CN (1) CN100477123C (enExample)
TW (1) TWI307532B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007281038A (ja) * 2006-04-03 2007-10-25 Toshiba Corp 半導体装置
JP5287621B2 (ja) * 2009-09-10 2013-09-11 富士通セミコンダクター株式会社 半導体装置
CN103794559A (zh) * 2012-10-29 2014-05-14 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
CN104217953B (zh) * 2013-06-05 2017-06-13 中芯国际集成电路制造(上海)有限公司 Pmos晶体管及其制作方法
CN104425281B (zh) * 2013-09-09 2018-08-24 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US9281196B2 (en) * 2013-12-31 2016-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method to reduce etch variation using ion implantation
CN105990142A (zh) * 2015-02-03 2016-10-05 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其制作方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0459763B1 (en) * 1990-05-29 1997-05-02 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistors
JPH06310719A (ja) * 1993-04-19 1994-11-04 Sharp Corp Ｇｅ−ＳｉのＳＯＩ型ＭＯＳトランジスタ及びその製造方法
US5572040A (en) * 1993-07-12 1996-11-05 Peregrine Semiconductor Corporation High-frequency wireless communication system on a single ultrathin silicon on sapphire chip
JPH10326837A (ja) * 1997-03-25 1998-12-08 Toshiba Corp 半導体集積回路装置の製造方法、半導体集積回路装置、半導体装置、及び、半導体装置の製造方法
US5869359A (en) * 1997-08-20 1999-02-09 Prabhakar; Venkatraman Process for forming silicon on insulator devices having elevated source and drain regions
US6541343B1 (en) * 1999-12-30 2003-04-01 Intel Corporation Methods of making field effect transistor structure with partially isolated source/drain junctions
US6633066B1 (en) 2000-01-07 2003-10-14 Samsung Electronics Co., Ltd. CMOS integrated circuit devices and substrates having unstrained silicon active layers
US6303450B1 (en) * 2000-11-21 2001-10-16 International Business Machines Corporation CMOS device structures and method of making same
US6593625B2 (en) 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
JP3626734B2 (ja) * 2002-03-11 2005-03-09 日本電気株式会社 薄膜半導体装置
US6780686B2 (en) * 2002-03-21 2004-08-24 Advanced Micro Devices, Inc. Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions
TW530385B (en) 2002-03-27 2003-05-01 Taiwan Semiconductor Mfg CMOS with strain-balanced structure and method of manufacturing the same
US6921913B2 (en) * 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
US6911379B2 (en) 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate
CN1303656C (zh) * 2004-06-18 2007-03-07 北京大学 一种准soi场效应晶体管器件的制备方法
US7138309B2 (en) * 2005-01-19 2006-11-21 Sharp Laboratories Of America, Inc. Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer

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