CN100477123C - 用于减小多晶硅高度的SOI底部预掺杂合并e-SiGe - Google Patents
用于减小多晶硅高度的SOI底部预掺杂合并e-SiGe Download PDFInfo
- Publication number
- CN100477123C CN100477123C CNB200610075110XA CN200610075110A CN100477123C CN 100477123 C CN100477123 C CN 100477123C CN B200610075110X A CNB200610075110X A CN B200610075110XA CN 200610075110 A CN200610075110 A CN 200610075110A CN 100477123 C CN100477123 C CN 100477123C
- Authority
- CN
- China
- Prior art keywords
- silicon body
- doping
- layer
- transistor
- boron
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
- H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
- H10D30/875—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] having thin-film semiconductor bodies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
- H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having non-planar bodies, e.g. having recessed gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/107,843 | 2005-04-18 | ||
| US11/107,843 US7605042B2 (en) | 2005-04-18 | 2005-04-18 | SOI bottom pre-doping merged e-SiGe for poly height reduction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1855391A CN1855391A (zh) | 2006-11-01 |
| CN100477123C true CN100477123C (zh) | 2009-04-08 |
Family
ID=37109033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200610075110XA Expired - Fee Related CN100477123C (zh) | 2005-04-18 | 2006-04-18 | 用于减小多晶硅高度的SOI底部预掺杂合并e-SiGe |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7605042B2 (enExample) |
| JP (1) | JP2006319326A (enExample) |
| CN (1) | CN100477123C (enExample) |
| TW (1) | TWI307532B (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425281B (zh) * | 2013-09-09 | 2018-08-24 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007281038A (ja) * | 2006-04-03 | 2007-10-25 | Toshiba Corp | 半導体装置 |
| JP5287621B2 (ja) | 2009-09-10 | 2013-09-11 | 富士通セミコンダクター株式会社 | 半導体装置 |
| CN103794559A (zh) * | 2012-10-29 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制备方法 |
| CN104217953B (zh) * | 2013-06-05 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | Pmos晶体管及其制作方法 |
| US9281196B2 (en) * | 2013-12-31 | 2016-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to reduce etch variation using ion implantation |
| CN105990142A (zh) * | 2015-02-03 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管及其制作方法 |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5663570A (en) * | 1993-07-12 | 1997-09-02 | Peregrine Semiconductor Corporation | High-frequency wireless communication system on a single ultrathin silicon on sapphire chip |
| US5869359A (en) * | 1997-08-20 | 1999-02-09 | Prabhakar; Venkatraman | Process for forming silicon on insulator devices having elevated source and drain regions |
| US6051509A (en) * | 1997-03-25 | 2000-04-18 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit manufacturing method and device |
| CN1437769A (zh) * | 1999-12-30 | 2003-08-20 | 英特尔公司 | 具有部分隔离的源/漏结的场效应晶体管结构及其制造方法 |
| CN1444281A (zh) * | 2002-03-11 | 2003-09-24 | 日本电气株式会社 | 薄膜半导体器件及其制造该器件的方法 |
| CN1527379A (zh) * | 2003-03-04 | 2004-09-08 | ̨������·����ɷ�����˾ | 具有晶格不相称区的变形沟道晶体管结构及其制造方法 |
| CN1595624A (zh) * | 2004-06-18 | 2005-03-16 | 北京大学 | 一种准soi场效应晶体管器件的制备方法 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0459763B1 (en) * | 1990-05-29 | 1997-05-02 | Semiconductor Energy Laboratory Co., Ltd. | Thin-film transistors |
| JPH06310719A (ja) * | 1993-04-19 | 1994-11-04 | Sharp Corp | Ge−SiのSOI型MOSトランジスタ及びその製造方法 |
| US6633066B1 (en) | 2000-01-07 | 2003-10-14 | Samsung Electronics Co., Ltd. | CMOS integrated circuit devices and substrates having unstrained silicon active layers |
| US6303450B1 (en) * | 2000-11-21 | 2001-10-16 | International Business Machines Corporation | CMOS device structures and method of making same |
| US6593625B2 (en) | 2001-06-12 | 2003-07-15 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
| US6780686B2 (en) * | 2002-03-21 | 2004-08-24 | Advanced Micro Devices, Inc. | Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions |
| TW530385B (en) | 2002-03-27 | 2003-05-01 | Taiwan Semiconductor Mfg | CMOS with strain-balanced structure and method of manufacturing the same |
| US6911379B2 (en) | 2003-03-05 | 2005-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming strained silicon on insulator substrate |
| US7138309B2 (en) * | 2005-01-19 | 2006-11-21 | Sharp Laboratories Of America, Inc. | Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer |
-
2005
- 2005-04-18 US US11/107,843 patent/US7605042B2/en not_active Expired - Fee Related
-
2006
- 2006-03-30 TW TW095111288A patent/TWI307532B/zh not_active IP Right Cessation
- 2006-04-18 CN CNB200610075110XA patent/CN100477123C/zh not_active Expired - Fee Related
- 2006-04-18 JP JP2006114623A patent/JP2006319326A/ja not_active Abandoned
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5663570A (en) * | 1993-07-12 | 1997-09-02 | Peregrine Semiconductor Corporation | High-frequency wireless communication system on a single ultrathin silicon on sapphire chip |
| US6051509A (en) * | 1997-03-25 | 2000-04-18 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit manufacturing method and device |
| US5869359A (en) * | 1997-08-20 | 1999-02-09 | Prabhakar; Venkatraman | Process for forming silicon on insulator devices having elevated source and drain regions |
| CN1437769A (zh) * | 1999-12-30 | 2003-08-20 | 英特尔公司 | 具有部分隔离的源/漏结的场效应晶体管结构及其制造方法 |
| CN1444281A (zh) * | 2002-03-11 | 2003-09-24 | 日本电气株式会社 | 薄膜半导体器件及其制造该器件的方法 |
| CN1527379A (zh) * | 2003-03-04 | 2004-09-08 | ̨������·����ɷ�����˾ | 具有晶格不相称区的变形沟道晶体管结构及其制造方法 |
| CN1595624A (zh) * | 2004-06-18 | 2005-03-16 | 北京大学 | 一种准soi场效应晶体管器件的制备方法 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425281B (zh) * | 2013-09-09 | 2018-08-24 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US7605042B2 (en) | 2009-10-20 |
| TW200644129A (en) | 2006-12-16 |
| US20060234432A1 (en) | 2006-10-19 |
| CN1855391A (zh) | 2006-11-01 |
| TWI307532B (en) | 2009-03-11 |
| JP2006319326A (ja) | 2006-11-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE102006029281B4 (de) | Halbleiterbauelement mit einer vergrabenen Gateelektrode und Verfahren zu seiner Herstellung | |
| US8445939B2 (en) | Method of forming a semiconductor device and semiconductor device | |
| US8278179B2 (en) | LDD epitaxy for FinFETs | |
| JP4439486B2 (ja) | 半導体装置 | |
| US8941153B2 (en) | FinFETs with different fin heights | |
| KR101811796B1 (ko) | 급경사 접합 프로파일을 갖는 소스/드레인 영역들을 구비하는 반도체 소자 및 그 제조방법 | |
| US7700452B2 (en) | Strained channel transistor | |
| US7453120B2 (en) | Semiconductor structure | |
| US20130316509A1 (en) | Semiconductor Device Manufacturing Method | |
| KR20040098302A (ko) | 엘리베이티드 소오스/드레인 구조의 모스트랜지스터 및 그제조방법 | |
| US9111785B2 (en) | Semiconductor structure with improved channel stack and method for fabrication thereof | |
| CN103715194B (zh) | 半导体集成电路器件及其制造方法 | |
| US6696729B2 (en) | Semiconductor device having diffusion regions with different junction depths | |
| US8318571B2 (en) | Method for forming P-type lightly doped drain region using germanium pre-amorphous treatment | |
| WO2012062791A1 (en) | Creating anisotrpically diffused junctions in field effect transistor devices | |
| JP2012059783A (ja) | 半導体装置の製造方法 | |
| US7943471B1 (en) | Diode with asymmetric silicon germanium anode | |
| US20070029608A1 (en) | Offset spacers for CMOS transistors | |
| CN100477123C (zh) | 用于减小多晶硅高度的SOI底部预掺杂合并e-SiGe | |
| US20050184335A1 (en) | Semiconductor device and fabricating method thereof | |
| US8377781B2 (en) | Transistor with asymmetric silicon germanium source region | |
| US20120231591A1 (en) | Methods for fabricating cmos integrated circuits having metal silicide contacts | |
| US20090250771A1 (en) | Mosfet and production method of semiconductor device | |
| US7915128B2 (en) | High voltage semiconductor devices | |
| US20070069309A1 (en) | Buried well for semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090408 Termination date: 20130418 |