CN1855391A - 用于减小多晶硅高度的SOI底部预掺杂合并e－SiGe - Google Patents

用于减小多晶硅高度的SOI底部预掺杂合并e－SiGe Download PDF

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CN1855391A
CN1855391A CNA200610075110XA CN200610075110A CN1855391A CN 1855391 A CN1855391 A CN 1855391A CN A200610075110X A CNA200610075110X A CN A200610075110XA CN 200610075110 A CN200610075110 A CN 200610075110A CN 1855391 A CN1855391 A CN 1855391A
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silicon body
grid
transistor
boron
semiconductor device
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幸山裕亮
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Abstract

描述了半导体器件结构和制作该结构的方法，该结构提供有完全掺杂的晶体管源/漏区，同时减少甚至避免硼穿透进入晶体管沟道，从而改善了晶体管的性能。此外，这种晶体管受益于对晶体管沟道施加压应力的SiGe层(401)，从而进一步改善了晶体管的性能。

Description

用于减小多晶硅高度的SOI底部预掺杂合并e-SiGe
技术领域
本发明的各方面一般地涉及半导体器件及其制造方法，并且更具体地涉及提供一种对晶体管的源/漏区掺杂同时减少硼穿透进入晶体管沟道的途径，并且也在同一晶体管中提供了向晶体管沟道施加压应力的SiGe层。
背景技术
各种类型的硅晶体管经常包括多晶硅栅。存在着许多影响栅的合适高度的因素。例如，将栅制作得过高会导致诸如在最终产品中的不希望的寄生电容的问题以及注入遮蔽问题(implant shadowingproblem)(尤其在多个栅按照小尺度间距重复时)，以及导致在制造期间多晶硅蚀刻时的困难。因此，希望限制多晶硅栅的高度。
另一方面，将栅制作得过短会导致其它的问题，例如，在晶体管制造期间，存在着在或者允许不希望的硼穿透进入晶体管沟道、或者对晶体管的源/漏区掺杂不充分之间的折衷。例如，参照图1，所说明的传统硅器件具有包括硅本体1、硅本体1紧邻下面的埋置氧化物(BOX)层4和BOX层4下面的衬底(未示出)的绝缘体上硅(SOI)晶片结构。该器件具有包括多晶硅栅2和源/漏区3的晶体管。为了产生源/漏区3，该区域由硼离子来掺杂。栅2也同时由硼离子来掺杂。在图1中，为了避免硼离子穿透进入栅2下方的的沟道中，采用低能量剂量的硼离子。尽管成功地避免了沟道硼穿透，但低能量剂量的副作用是源/漏区3没有被充分掺杂使其毗邻BOX层4。换句话说，在源/漏区3和BOX层4之间存在着间隙。这会导致不希望的高结电容。
参照图2，这次采用更高能量剂量的硼离子。结果，现在源/漏区3合适地毗邻BOX层4，因此降低了结电容。然而，为了充分掺杂源/漏区3，副作用是硼离子已经完全穿透栅2而进入下方硅本体1的沟道部分。这种沟道硼穿透导致沟道迁移率的极大恶化，这是非常不希望的。因此，需要一种充分掺杂晶体管源/漏区而又不允许不希望量的硼离子穿透进入沟道的途径。
此外，已经发现在晶体管的栅和沟道的相对侧面使用硅锗(SiGe)层可以明显地改善晶体管的性能。这是由通过SiGe层作用在沟道上的压力而导致的。因此，也希望找到一种途径制造包括这样的SiGe层的晶体管，仍然对源/漏区完全掺杂而没有同时最小化或另外减少沟道硼穿透。
发明内容
本发明的一方面涉及诸如在绝缘体上硅(SOI)晶片上制造半导体器件的方法，该半导体器件具有源/漏区被硼离子充分掺杂同时减少或者甚至避免硼穿透晶体管沟道的晶体管。这可以得到具有优异工作特性的晶体管，如低结电容。可以不需要制造额外高的晶体管栅来制造这种器件，其可产生具有低寄生电容的晶体管，同时利用较简单和便宜的一组制造步骤。除了实现上述内容，该制造工艺还允许添加在晶体管沟道上提供压应力的硅锗(SiGe)层，从而提高P型晶体管沟道内的空穴迁移率。
本发明的另一方面涉及制造上述半导体器件的方法，使得上述晶体管是P型场效应晶体管(PFET)，其中该方法还允许在同一晶片上同时制造N型场效应晶体管(NFET)。
本发明的仍另一方面涉及由上述制造方法得到的半导体器件和/或晶体管。
在考虑以下对示例性实施方式的详细描述时，将清楚本发明的这些和其它方面。
附图说明
通过考虑附图参照下文的描述可以获得对本发明及其优点的更完整的理解，其中类似的参考数字表示类似的特征。
图1表示导致低剂量掺杂的对SOI器件的传统低能量硼掺杂。
图2表示导致高剂量掺杂的对SOI器件的传统高能量硼掺杂。
图3-6表示可以在制造具有外延SiGe层的SOI器件中进行的示例性主要步骤。
图7-22表示可以在制造具有外延SiGe层的另一SOI器件中进行的示例性步骤。
具体实施方式
现在将结合图3-6描述在示例性的制造工艺中的概述的重要某些步骤，所述附图按照在示例性工艺中执行的连续次序来显示。参照图3，所示出的传统SOI晶片的一部分包括硅本体301。在硅本体301上形成P型场效应晶体管(PFET)多晶硅栅302，在栅302的侧壁上形成侧壁隔层304。栅302也由SiN层303作为帽盖。硅本体301的凹陷部分305通过硼注入而预掺杂。随后，在图4中，在凹陷部分305上外延生长SiGe层401。在图5中执行扩展形成之后，然后在图6中，采用低能量的硼注入栅302和源/漏区，从而减少甚至避免硼穿透进入栅302下方的沟道。这种低能量的硼可以具有例如2-10KeV范围内的能量，如大约5KeV。
现在将结合图7-22讨论对示例性制造工艺的更详细的描述，所述附图按照在示例性工艺中执行的连续次序来显示。首先参照图7，所示出的传统SOI晶片的一部分包括具有嵌入的浅沟槽隔离(STI)层705的硅本体701。硅本体701可以是例如大约50-70纳米厚，而STI层705可以是例如大约60-80纳米厚。在BOX层710上设置硅本体701，STI层705稍微地延伸到BOX层710中。BOX层710可以是例如大约150纳米厚。BOX层710又设置在衬底(未示出)上。在STI层705的相对侧面，在硅本体701上按照传统的方式形成N型场效应晶体管(NFET)栅702和PFET栅703。栅702和703可以是例如大约100纳米高度或更小，并且可以设置在具有薄栅氧化物层(未示出)的硅本体701上。然后，按照传统的方式在栅702和703的顶部沉积第一SiN层，以形成帽盖707和708。帽盖707和708可以是例如大约50纳米厚度或更小。按照传统的方式，对栅702和703的侧壁再氧化(在栅702和703的侧壁上导致未示出的大约5纳米宽的再氧化层)，并在硅晶片的整个表面上沉积掩模层704(如第二SiN层)。掩模层704可以是例如大约40纳米的厚度。随后，SOI晶片由光致抗蚀剂层706覆盖，对其曝光和蚀刻从而仅覆盖NFET区域。随后，使用经图形化的光致抗蚀剂层706作为掩模执行传统的反应离子蚀刻(RIE)，得到PFET栅703的侧壁上的侧壁隔层709。侧壁隔层709可以各为例如大约40纳米的宽度。
参照图8，去除光致抗蚀剂层706。然后，采用掩模层704和帽盖708作为掩模，通过传统的RIE选择性的凹陷硅本体701的暴露部分，以得到各具有凹陷801的凹陷部分802。凹陷801可以是例如进入硅本体701大约40-60纳米的深度，使得剩余的凹陷部分802为例如大约10纳米的厚度。
参照图9，然后向硅本体701中凹陷区801的下表面901和侧壁902中注入硼，得到表面901和902下面的硼掺杂P型区。例如，可以采用大约3KeV、1×1015cm-2、偏离法线大约15度的角度的二氟化硼(BF2)注入。这种硼“预掺杂”允许在图20中说明的随后掺杂步骤中采用更低的能量剂量的硼。
参照图10，然后在凹陷区801上外延生长SiGe层1001。SiGe层1001可以是例如大约50-70纳米的厚度。此外，在该外延生长期间或之后，在表面901和902下面的掺硼P型区中至少一些硼扩散到SiGe层1001中，在图10中由SiGe层1001的较暗部分表示。此外，表面901下方的至少一些硼扩散到硅本体701中，使得硼毗邻BOX层710。表面902附近另外的更多的硼轻微地朝沟道扩散，如图10所示。SiGe层1001对栅703下方的PFET沟道提供压应力，从而改善了PFET的性能。
参照图11，然后去除掩模层704和帽盖707、708。
参照图12，然后在栅702、703的侧壁上形成偏置隔层(offsetspacer)(如第一氧化物层)1201。偏置隔层1201各自可以延伸栅702、703的相应的长度，并且可以各自是例如大约10纳米的宽度。
参照图13和14，然后采用光致抗蚀剂掩模层1302和1401，在区域1301中的NFET上和在PFET(在区域1402中)分别选择性地执行N型扩展和P型晕圈注入(halo implantation)。通常，扩展注入可以是比晕圈注入更高的剂量。例如，在NFET区，采用大约2KeV、2×1015cm-2的砷(As)扩展注入，以及采用大约10KeV、8×1013cm-2、偏离法线大约30度角度的硼(B)晕圈注入。并且，在PFET区，采用例如大约3KeV、1×1015cm-2的二氟化硼(BF2)扩展注入，以及采用大约60KeV、5×1013cm-2、偏离法线大约30度角度的砷(As)晕圈注入。随后可以分别去除光致抗蚀剂掩模层1302、1401。
参照图15，然后在晶片上沉积第三SiN层1501。第三SiN层1501可以是例如大约50纳米的厚度。随后，采用传统的覆盖RIE技术，在第三SiN层1501上形成另一组偏置隔层(如第二氧化物层)1502。这些偏置隔层1502可以各自是例如大约40纳米的宽度。
参照图16，然后采用光致抗蚀剂掩模层1601，仅在NFET上执行深源/漏注入。例如，可以采用45Kev、1×1015cm-2的磷(P)注入。如同可以看到的那样，由于高能量的磷穿过第三SiN层1501而形成了区域1602。
参照图17，然后从NFET(但不从PFET)去除偏置隔层1502。
参照图18，在NFET栅702的相对侧面上形成窄隔层1801，并通过在第三SiN层1501上执行传统的覆盖RIE而在PFET栅703的相对侧面上形成堆叠的宽隔层1802。窄隔层1801可以是例如大约40纳米的宽度，而宽隔层1802可以是例如大约90纳米的宽度。
参照图19和20，分别采用光致抗蚀剂掩模层1901和2001在NFET和PFET上执行源/漏掺杂。采用浅或轻注入(导致少量或没有硼穿透进入栅703)，执行PFET的P型掺杂。这是可行的，因为结合图9已经发生了对PFET的源/漏区的预掺杂。例如，在NFET区中，可以采用大约15KeV、2×1015cm-2的砷(As)注入，而在PFET区中，可以采用大约5KeV、2.5×1015cm-2的二氟化硼(BF2)注入。然后在各自分别的注入之后去除光致抗蚀剂层1901、2001。作为重N型掺杂的结果，如图19所示形了区域1902。同样，作为浅P型掺杂的结果，如图20所示形成了区域2002。通过执行这些步骤，不然之后可能发生的硼穿透进入PFET栅703下方的沟道被明显地减少，甚至被完全避免。
参照图21，执行激活退火，使得栅703和704被很好地掺杂，分别得到被很好地掺杂的栅2101和2102以及NFET和PFET源/漏区，使得这些区域向下生长以毗邻硅本体701紧邻下方的BOX层710。
参照图22，在栅2101、2102以及NFET和PFET的源/漏区上形成硅化镍层2201。
因而已经描述了新结构和用于制作该结构的方法，该新结构提供有完全掺杂的晶体管源/漏区，同时减少甚至避免硼穿透进入晶体管沟道，从而改善晶体管的性能。此外，这样的晶体管可以受益于对晶体管沟道施加压应力的SiGe层，从而进一步改善了晶体管的性能。

Claims (14)

1.一种用于形成半导体器件的方法，特征在于包括：
在硅本体上形成晶体管栅；
在栅的相对侧面上形成硅本体的凹陷部分；
对该凹陷部分执行第一掺杂；
在执行第一掺杂的步骤之后，在凹陷部分上形成SiGe层；以及
在形成SiGe层之后，对栅执行第二掺杂。
2.根据权利要求1的方法，特征在于所述执行第一掺杂的步骤包括在所述凹陷部分上以大约3KeV、1×1015cm-2执行BF2注入。
3.根据权利要求2的方法，特征在于所述执行第二掺杂的步骤包括以大约5KeV、2.5×1015cm-2执行BF2注入。
4.根据权利要求1的方法，特征在于所述执行第一掺杂的步骤包括对所述凹陷部分的每一个的下表面和侧壁二者掺杂。
5.根据权利要求1的方法，还包括：
在所述栅的相对侧面的每一个上形成侧壁隔层；以及
去除每个侧壁隔层；以及
执行扩展形成，
其中所述执行第一掺杂和形成凹陷部分的步骤在去除该侧壁隔层之前执行。
6.根据权利要求1的方法，特征在于在所述执行第一掺杂和第二掺杂的步骤二者中，在栅下方的硅本体中的晶体管沟道区不被硼渗透。
7.根据权利要求6的方法，特征在于所述晶体管栅包括多晶硅，并在所述硅本体上方延伸不大于大约100纳米。
8.根据权利要求6的方法，特征在于所述执行第二掺杂的步骤包括执行对栅的第二掺杂。
9.根据权利要求1的方法，特征在于所述硅本体被设置在埋置氧化物层的上方，并且其中执行第一掺杂的步骤在所述硅本体中得到各自毗邻该埋置氧化物层的一对源/漏区。
10.一种半导体器件，特征在于包括：
绝缘体上硅晶片，包括设置在埋置氧化物层上方的硅本体；以及
晶体管，包括：
设置在硅本体上凹陷之间的晶体管栅，
一对源/漏区，以及
硅本体中的沟道区，
其中该源/漏区采用硼离子来掺杂从而各自毗邻该埋置氧化物层，并且其中该沟道区不被硼离子穿透。
11.根据权利要求10的半导体器件，还包括设置在所述沟道区的相对侧面上所述硅本体的凹陷部分上的SiGe层。
12.根据权利要求10的半导体器件，特征在于所述源/漏区采用二氟化硼来掺杂。
13.根据权利要求10的半导体器件，特征在于所述晶体管栅采用硼离子来掺杂。
14.根据权利要求10的半导体器件，特征在于所述晶体管栅包括多晶硅，并在所述硅本体上方延伸不大于大约100纳米。
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