JP2006286797A - 実装方法 - Google Patents
実装方法 Download PDFInfo
- Publication number
- JP2006286797A JP2006286797A JP2005102748A JP2005102748A JP2006286797A JP 2006286797 A JP2006286797 A JP 2006286797A JP 2005102748 A JP2005102748 A JP 2005102748A JP 2005102748 A JP2005102748 A JP 2005102748A JP 2006286797 A JP2006286797 A JP 2006286797A
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- JP
- Japan
- Prior art keywords
- resin
- electronic component
- substrate
- hole
- mounting method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】基板に電子部品を実装するに際し、基板と電子部品との間の間隙にアンダーフィル剤としての樹脂を充填するに際し、電子部品に、その厚み方向に貫通するスルーホールを形成し、スルーホールを通して樹脂を充填することを特徴とする実装方法。
【選択図】図1
Description
図1は、本発明の一実施態様に係る実装方法を示している。図1において、1は電極2を備えた基板を、3はバンプ4を備えた電子部品としてのチップを示している。この基板1の電極2に、チップ3のバンプ4を接合するに際し、基板1とチップ3の間に所定の間隙5が形成され、この間隙5にアンダーフィル剤としての樹脂6が充填される。
2 電極
3 電子部品としてのチップ
4 バンプ
5 間隙
6 樹脂
7 スルーホール
8 ニードル
Claims (5)
- 基板に電子部品を実装するに際し、基板と電子部品との間の間隙に樹脂を充填する実装方法において、電子部品に、その厚み方向に貫通するスルーホールを形成し、該スルーホールを通して前記樹脂を充填することを特徴とする実装方法。
- 前記樹脂を注入するニードルを前記スルーホール内に挿入し、該ニードルから前記樹脂を充填する、請求項1の実装方法。
- 前記スルーホールの内径を前記ニードルの外径よりも大きく形成する、請求項2の実装方法。
- 前記スルーホールを、前記電子部品1個に対し、複数形成する、請求項1〜3のいずれかに記載の実装方法。
- 前記電子部品がチップからなる、請求項1〜4のいずれかに記載の実装方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005102748A JP2006286797A (ja) | 2005-03-31 | 2005-03-31 | 実装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005102748A JP2006286797A (ja) | 2005-03-31 | 2005-03-31 | 実装方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006286797A true JP2006286797A (ja) | 2006-10-19 |
Family
ID=37408394
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005102748A Pending JP2006286797A (ja) | 2005-03-31 | 2005-03-31 | 実装方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2006286797A (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014502133A (ja) * | 2010-11-02 | 2014-01-23 | エプコス アーゲー | アクチュエータユニットの製造方法及び圧電アクチュエータを収容するスリーブ |
CN104779175A (zh) * | 2014-01-15 | 2015-07-15 | 矽品精密工业股份有限公司 | 半导体封装件及其制法 |
US11107769B2 (en) | 2019-08-02 | 2021-08-31 | Samsung Electronics Co., Ltd. | Semiconductor package and a method of fabricating the same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06314715A (ja) * | 1993-04-28 | 1994-11-08 | Fujitsu Ltd | 半導体チップ及び半導体装置の製造方法 |
JP2001053090A (ja) * | 1999-07-15 | 2001-02-23 | Motorola Inc | 電子アセンブリのアンダフィリングを行う方法 |
JP2005135997A (ja) * | 2003-10-28 | 2005-05-26 | Fujikura Ltd | 電子部品の封止方法およびその電子部品 |
-
2005
- 2005-03-31 JP JP2005102748A patent/JP2006286797A/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06314715A (ja) * | 1993-04-28 | 1994-11-08 | Fujitsu Ltd | 半導体チップ及び半導体装置の製造方法 |
JP2001053090A (ja) * | 1999-07-15 | 2001-02-23 | Motorola Inc | 電子アセンブリのアンダフィリングを行う方法 |
JP2005135997A (ja) * | 2003-10-28 | 2005-05-26 | Fujikura Ltd | 電子部品の封止方法およびその電子部品 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014502133A (ja) * | 2010-11-02 | 2014-01-23 | エプコス アーゲー | アクチュエータユニットの製造方法及び圧電アクチュエータを収容するスリーブ |
US9412933B2 (en) | 2010-11-02 | 2016-08-09 | Epcos Ag | Method for producing an actuator unit and sleeve for receiving a piezoactuator |
CN104779175A (zh) * | 2014-01-15 | 2015-07-15 | 矽品精密工业股份有限公司 | 半导体封装件及其制法 |
US11107769B2 (en) | 2019-08-02 | 2021-08-31 | Samsung Electronics Co., Ltd. | Semiconductor package and a method of fabricating the same |
US11610845B2 (en) | 2019-08-02 | 2023-03-21 | Samsung Electronics Co., Ltd. | Semiconductor package and a method of fabricating the same |
US11996365B2 (en) | 2019-08-02 | 2024-05-28 | Samsung Electronics Co., Ltd. | Semiconductor package and a method of fabricating the same |
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