JP2006261549A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2006261549A JP2006261549A JP2005079603A JP2005079603A JP2006261549A JP 2006261549 A JP2006261549 A JP 2006261549A JP 2005079603 A JP2005079603 A JP 2005079603A JP 2005079603 A JP2005079603 A JP 2005079603A JP 2006261549 A JP2006261549 A JP 2006261549A
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- Prior art keywords
- substrate
- semiconductor device
- solder resist
- external connection
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
Landscapes
- Wire Bonding (AREA)
Abstract
【解決手段】半導体装置において、通常外部接続端子22以外の接合面はソルダーレジスト32により覆われているが、本発明においては、基板10端部から外部接続端子22の位置の領域にはソルダーレジスト32が配設されていないため、半導体装置が実装基板に実装された状態において、半導体装置の外部接続端子22と実装基板との接合部を側面より観察することが可能となる。
【選択図】図2
Description
2…半導体素子
4…電極パッド
6…ワイヤ
8…バンプ
10…基板
12…基材
14…内部配線部
20…ボンディングパッド
22…外部接続端子
24…上面表面配線部
26…下面表面配線部
28…配線接続部
30、32…ソルダーレジスト
34…開口部
40…接着剤
42…封止樹脂
50…半田ボール
Claims (5)
- 半導体素子と、
前記半導体素子が搭載された基板とを有する半導体装置において、
前記基板の前記半導体素子が搭載された第1の面とは反対の第2の面に複数のランド型の外部接続端子を有し,
前記第2の面には、前記外部接続端子の上を除いて半田レジストが配設されており,
前記半田レジストの前記外部接続端子部における半田レジスト開口部は前記基板外周端面に向かう方向に開口していることを特徴とする半導体装置。 - 請求項1記載の半導体装置において,
前記半田レジスト開口部の形状が,基板外周端部に向かう方向に開口幅が末広がりとなるような形状となっていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
基板外周端に沿って半田レジストが引き込んでいるように配設されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において,
半田レジスト開口部の端部における断面形状が,表面方向に広がる形状となっていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において,
前記ランド型の外部接続端子上に半田ボールが形成されていることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005079603A JP4828139B2 (ja) | 2005-03-18 | 2005-03-18 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005079603A JP4828139B2 (ja) | 2005-03-18 | 2005-03-18 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006261549A true JP2006261549A (ja) | 2006-09-28 |
JP4828139B2 JP4828139B2 (ja) | 2011-11-30 |
Family
ID=37100418
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005079603A Active JP4828139B2 (ja) | 2005-03-18 | 2005-03-18 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4828139B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007250675A (ja) * | 2006-03-14 | 2007-09-27 | Sanyo Electric Co Ltd | 回路基板及び半導体装置 |
JP2008116366A (ja) * | 2006-11-06 | 2008-05-22 | Fujitsu Ltd | 表面形状センサとその製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0653347A (ja) * | 1991-09-30 | 1994-02-25 | Ibiden Co Ltd | リードレスチップキャリア |
JP2002118204A (ja) * | 1999-11-17 | 2002-04-19 | Sumitomo Bakelite Co Ltd | 半導体装置、並びに半導体搭載用基板及びその製造方法 |
JP2004014893A (ja) * | 2002-06-10 | 2004-01-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
-
2005
- 2005-03-18 JP JP2005079603A patent/JP4828139B2/ja active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0653347A (ja) * | 1991-09-30 | 1994-02-25 | Ibiden Co Ltd | リードレスチップキャリア |
JP2002118204A (ja) * | 1999-11-17 | 2002-04-19 | Sumitomo Bakelite Co Ltd | 半導体装置、並びに半導体搭載用基板及びその製造方法 |
JP2004014893A (ja) * | 2002-06-10 | 2004-01-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007250675A (ja) * | 2006-03-14 | 2007-09-27 | Sanyo Electric Co Ltd | 回路基板及び半導体装置 |
JP2008116366A (ja) * | 2006-11-06 | 2008-05-22 | Fujitsu Ltd | 表面形状センサとその製造方法 |
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Publication number | Publication date |
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JP4828139B2 (ja) | 2011-11-30 |
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