JP2006261269A - 接続孔形成法 - Google Patents
接続孔形成法 Download PDFInfo
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- JP2006261269A JP2006261269A JP2005074488A JP2005074488A JP2006261269A JP 2006261269 A JP2006261269 A JP 2006261269A JP 2005074488 A JP2005074488 A JP 2005074488A JP 2005074488 A JP2005074488 A JP 2005074488A JP 2006261269 A JP2006261269 A JP 2006261269A
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- insulating film
- connection hole
- etching
- wiring layer
- film
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- 238000000034 method Methods 0.000 title claims description 61
- 239000010410 layer Substances 0.000 claims abstract description 70
- 238000005530 etching Methods 0.000 claims abstract description 43
- 238000001312 dry etching Methods 0.000 claims abstract description 38
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 239000011248 coating agent Substances 0.000 claims abstract description 24
- 238000000576 coating method Methods 0.000 claims abstract description 24
- 230000008021 deposition Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims description 33
- 239000007789 gas Substances 0.000 claims description 23
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 3
- 230000002265 prevention Effects 0.000 abstract 1
- 239000004576 sand Substances 0.000 abstract 1
- 229920000642 polymer Polymers 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910052718 tin Inorganic materials 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000001629 suppression Effects 0.000 description 6
- 229910010282 TiON Inorganic materials 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910010060 TiBN Inorganic materials 0.000 description 1
- -1 TiN Chemical class 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002893 slag Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
【解決手段】半導体基板10の一主面を覆う絶縁膜12の上にTiN等の反射防止膜14cを有する配線層14を形成した後、配線層14を覆って絶縁膜16a〜16cを含む層間絶縁膜を形成する。絶縁膜16a,16cは、プラズマCVD法等により形成したシリコン酸化膜からなり、絶縁膜16bは、無機又は有機SOG等の塗布絶縁膜からなる。レジスト層18をマスクとするドライエッチング処理により配線層14の一部に対応する接続孔20を層間絶縁膜に形成する際に、サイドエッチが進行しやすい絶縁膜16bまではN2を含まないデポジション性の強い条件でエッチングを行い、その後はN2を含むデポジション性の弱いい条件で絶縁膜16aのエッチングを行なう。
【選択図】図3
Description
基板の一主面を覆う絶縁膜の上に配線層を形成する工程と、
前記絶縁膜の上に前記配線層を覆って下から順に堆積絶縁膜及び塗布絶縁膜を重ねた積層膜を含む層間絶縁膜を形成する工程と、
選択的ドライエッチング処理により前記配線層の一部に対応する接続孔を前記層間絶縁膜に形成する工程であって、前記選択的ドライエッチング処理を少なくとも第1及び第2ステップを含む複数ステップで行ない、前記第1ステップではデポジション性の強い条件で前記塗布絶縁膜までのエッチングを行ない、前記第2ステップではデポジション性の弱い条件で前記堆積絶縁膜のエッチングを行なうものと
を含むものである。
ガス流量:CF4/CHF3=20〜50/80〜100[sccm]
(好ましくは30/90[sccm])
RFパワー:750[W]
圧力:200[mTorr]
とすることができる。
ガス流量:CF4/CHF3/N2=20〜50/80〜100/3〜10
[sccm](好ましくは30/90/4〜5[sccm])
RFパワー:750[W]
圧力:200[mTorr]
とすることができる。
Claims (5)
- 基板の一主面を覆う絶縁膜の上に配線層を形成する工程と、
前記絶縁膜の上に前記配線層を覆って下から順に堆積絶縁膜及び塗布絶縁膜を重ねた積層膜を含む層間絶縁膜を形成する工程と、
選択的ドライエッチング処理により前記配線層の一部に対応する接続孔を前記層間絶縁膜に形成する工程であって、前記選択的ドライエッチング処理を少なくとも第1及び第2ステップを含む複数ステップで行ない、前記第1ステップではデポジション性の強い条件で前記塗布絶縁膜までのエッチングを行ない、前記第2ステップではデポジション性の弱い条件で前記堆積絶縁膜のエッチングを行なうものと
を含む接続孔形成法。 - 前記選択的ドライエッチング処理では前記第1ステップのエッチングの後前記層間絶縁膜を大気にさらすことなく前記第2ステップのエッチングを行なう請求項1記載の接続孔形成法。
- 前記第1ステップのエッチングではエッチングガスとして窒素非含有のフルオロカーボン系ガスを用いると共に前記第2ステップのエッチングでは窒素含有のフルオロカーボン系ガスを用いる請求項1又は2記載の接続孔形成法。
- 前記配線層を形成する工程では前記配線層としてチタン含有化合物からなる導電層を最上層に有する配線層を形成する請求項3記載の接続孔形成法。
- 前記層間絶縁膜を形成する工程では前記塗布絶縁膜として無機スピンオンガラス膜又は有機スピンオンガラス膜を形成する請求項4記載の接続孔形成法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005074488A JP4543976B2 (ja) | 2005-03-16 | 2005-03-16 | 接続孔形成法 |
US11/373,999 US7557045B2 (en) | 2005-03-16 | 2006-03-14 | Manufacture of semiconductor device with good contact holes |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005074488A JP4543976B2 (ja) | 2005-03-16 | 2005-03-16 | 接続孔形成法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006261269A true JP2006261269A (ja) | 2006-09-28 |
JP4543976B2 JP4543976B2 (ja) | 2010-09-15 |
Family
ID=37010938
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2005074488A Expired - Fee Related JP4543976B2 (ja) | 2005-03-16 | 2005-03-16 | 接続孔形成法 |
Country Status (2)
Country | Link |
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US (1) | US7557045B2 (ja) |
JP (1) | JP4543976B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070264829A1 (en) * | 2006-05-12 | 2007-11-15 | Hynix Semiconductor Inc. | Slurry and method for chemical mechanical polishing |
JP2009049078A (ja) * | 2007-08-15 | 2009-03-05 | Elpida Memory Inc | 半導体装置の製造方法 |
CN114843221A (zh) * | 2021-02-02 | 2022-08-02 | 芯恩(青岛)集成电路有限公司 | 一种cmos器件的接触孔刻蚀方法及cmos器件制造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1041274A (ja) * | 1996-04-29 | 1998-02-13 | Applied Materials Inc | 誘電層のエッチング方法 |
JP2000077396A (ja) * | 1998-09-01 | 2000-03-14 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |
JP2000340549A (ja) * | 1999-06-01 | 2000-12-08 | Canon Inc | エッチング方法及びそれを用いた半導体装置の製造方法 |
JP2001351974A (ja) * | 2000-06-08 | 2001-12-21 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2002009058A (ja) * | 2000-06-26 | 2002-01-11 | Tokyo Electron Ltd | エッチング方法 |
JP2003282709A (ja) * | 2002-01-09 | 2003-10-03 | Hynix Semiconductor Inc | 半導体素子の多層金属配線形成方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001077086A (ja) | 1999-08-31 | 2001-03-23 | Oki Electric Ind Co Ltd | 半導体装置のドライエッチング方法 |
KR100350811B1 (ko) * | 2000-08-19 | 2002-09-05 | 삼성전자 주식회사 | 반도체 장치의 금속 비아 콘택 및 그 형성방법 |
US7067435B2 (en) * | 2004-09-29 | 2006-06-27 | Texas Instruments Incorporated | Method for etch-stop layer etching during damascene dielectric etching with low polymerization |
-
2005
- 2005-03-16 JP JP2005074488A patent/JP4543976B2/ja not_active Expired - Fee Related
-
2006
- 2006-03-14 US US11/373,999 patent/US7557045B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1041274A (ja) * | 1996-04-29 | 1998-02-13 | Applied Materials Inc | 誘電層のエッチング方法 |
JP2000077396A (ja) * | 1998-09-01 | 2000-03-14 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |
JP2000340549A (ja) * | 1999-06-01 | 2000-12-08 | Canon Inc | エッチング方法及びそれを用いた半導体装置の製造方法 |
JP2001351974A (ja) * | 2000-06-08 | 2001-12-21 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2002009058A (ja) * | 2000-06-26 | 2002-01-11 | Tokyo Electron Ltd | エッチング方法 |
JP2003282709A (ja) * | 2002-01-09 | 2003-10-03 | Hynix Semiconductor Inc | 半導体素子の多層金属配線形成方法 |
Also Published As
Publication number | Publication date |
---|---|
JP4543976B2 (ja) | 2010-09-15 |
US20060211238A1 (en) | 2006-09-21 |
US7557045B2 (en) | 2009-07-07 |
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