JP2006121094A5 - - Google Patents

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Publication number
JP2006121094A5
JP2006121094A5 JP2005307440A JP2005307440A JP2006121094A5 JP 2006121094 A5 JP2006121094 A5 JP 2006121094A5 JP 2005307440 A JP2005307440 A JP 2005307440A JP 2005307440 A JP2005307440 A JP 2005307440A JP 2006121094 A5 JP2006121094 A5 JP 2006121094A5
Authority
JP
Japan
Prior art keywords
charge trapping
gate electrode
dielectric film
trapping structure
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005307440A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006121094A (ja
JP5143350B2 (ja
Filing date
Publication date
Priority claimed from KR1020050001267A external-priority patent/KR100714473B1/ko
Priority claimed from US11/167,051 external-priority patent/US7446371B2/en
Application filed filed Critical
Publication of JP2006121094A publication Critical patent/JP2006121094A/ja
Publication of JP2006121094A5 publication Critical patent/JP2006121094A5/ja
Application granted granted Critical
Publication of JP5143350B2 publication Critical patent/JP5143350B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2005307440A 2004-10-21 2005-10-21 電荷トラップ膜を有する不揮発性メモリセル構造物及びその製造方法 Expired - Fee Related JP5143350B2 (ja)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US62081104P 2004-10-21 2004-10-21
US60/620,811 2004-10-21
KR10-2005-0001267 2005-01-06
KR1020050001267A KR100714473B1 (ko) 2004-10-21 2005-01-06 비휘발성 메모리 소자 및 그 제조 방법
US11/167,051 2005-06-24
US11/167,051 US7446371B2 (en) 2004-10-21 2005-06-24 Non-volatile memory cell structure with charge trapping layers and method of fabricating the same

Publications (3)

Publication Number Publication Date
JP2006121094A JP2006121094A (ja) 2006-05-11
JP2006121094A5 true JP2006121094A5 (enExample) 2008-11-27
JP5143350B2 JP5143350B2 (ja) 2013-02-13

Family

ID=46124068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005307440A Expired - Fee Related JP5143350B2 (ja) 2004-10-21 2005-10-21 電荷トラップ膜を有する不揮発性メモリセル構造物及びその製造方法

Country Status (2)

Country Link
JP (1) JP5143350B2 (enExample)
DE (1) DE102005051492B4 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007158093A (ja) * 2005-12-06 2007-06-21 Sony Corp 不揮発性半導体メモリデバイス及びその製造方法
JP5205011B2 (ja) 2007-08-24 2013-06-05 ルネサスエレクトロニクス株式会社 不揮発性半導体装置およびその製造方法
JP4599421B2 (ja) * 2008-03-03 2010-12-15 株式会社東芝 半導体装置及びその製造方法
JP2011071334A (ja) * 2009-09-25 2011-04-07 Toshiba Corp 不揮発性半導体記憶装置
JP2013058810A (ja) * 2012-12-27 2013-03-28 Renesas Electronics Corp 不揮発性半導体装置およびその製造方法
JP6510289B2 (ja) * 2015-03-30 2019-05-08 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06318709A (ja) * 1993-03-12 1994-11-15 Citizen Watch Co Ltd 半導体不揮発性記憶装置およびその製造方法
JP4923321B2 (ja) * 2000-09-12 2012-04-25 ソニー株式会社 不揮発性半導体記憶装置の動作方法
US6531350B2 (en) * 2001-02-22 2003-03-11 Halo, Inc. Twin MONOS cell fabrication method and array organization
US6639271B1 (en) * 2001-12-20 2003-10-28 Advanced Micro Devices, Inc. Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
US6756271B1 (en) * 2002-03-12 2004-06-29 Halo Lsi, Inc. Simplified twin monos fabrication method with three extra masks to standard CMOS
JP4647175B2 (ja) * 2002-04-18 2011-03-09 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JP2004303918A (ja) * 2003-03-31 2004-10-28 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP2005064178A (ja) * 2003-08-11 2005-03-10 Renesas Technology Corp 半導体装置およびその製造方法

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