JP2006086283A - 半導体搭載用リードピン - Google Patents
半導体搭載用リードピン Download PDFInfo
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Abstract
【解決手段】 図3(A)に示すように電極パッド44と半導体搭載用リードピンの鍔20との間の半田48内にボイドBが残ることがある。ICチップを搭載するためリフローを行った際に、接続用の半田48側も溶融すると共に、半田内のボイドBが膨張する。図3(B)に示すように溝部24に沿って側方へ抜けていくため、ボイドBにより鍔20が持ち上げられて、半導体搭載用リードピン10が傾くことが無くなる。
【選択図】 図3
Description
T型ピンのプル強度を向上させる技術が特許文献1中に開示されている。
図10(A)はパッケージ基板40を示している。パッケージ基板40の上面の電極パッド42には半田バンプ46が形成され、下面側の電極パッド44には半田48を介して半導体搭載用リードピン10が取り付けられている。ここで、図10(B)に示すように、パッケージ基板40の上面の半田バンプ46をリフローにより溶融してICチップ50の電極パッド52に接続させてICチップ50を搭載する際に、半導体搭載用リードピン10が傾斜することがあった。
前記鍔が、被接続パッドに当接可能な面状の平坦部と、該平坦部から凹んだ3以上の溝部とから成り、
平坦部が鍔の中央位置から側端まで延在すると共に、前記軸の中心を通る所定の垂線に対して対称に成るように形成され、溝部が側端から中央側に向けて形成されていることを技術的特徴とする。
以下、本発明の第1実施形態に係る半導体搭載用リードピンを図1〜図4を参照して説明する。
図1(A)は、本発明の第1実施形態に係る半導体搭載用リードピンの平面図であり、図1(B)は側面であり、図1(C)は斜視図である。
半導体搭載用リードピン10は、円筒状の軸12と円形平板状の鍔20とからなる。鍔20は、パッケージ基板の電極パッドに当接可能な面状の平坦部22と、該平坦部22から略半円状に凹んだ4つの溝部24とから成る。平坦部22は、鍔20の中央位置から側端20Eまで延在すると共に、軸12の中心CNと溝部24の最も深い部位とを通る垂線VLに対して対称に成るように形成されている。溝部24は側端20Eから中央側に向けて形成されている。
図2は、パッケージ基板への半導体搭載用リードピンの取り付け、及び、ICチップの搭載の工程を示す工程図である。図2(A)に示すように、パッケージ基板40の上面の電極パッド42には半田バンプ46が形成され、下面側の電極パッド44には接続用の半田ペースト48−aが配置されている。ここで、図2(B)に示すように、半田ペースト48−aをリフローにより溶解することで、パッケージ基板の下面に半導体搭載用リードピン10が取り付ける。そして、図2(C)に示すように、パッケージ基板40の上面の半田バンプ46をリフローにより溶融してICチップ50の電極パッド52に接続させる。
図1を参照して上述した第1実施形態の半導体搭載用リードピン10では、鍔20の溝部24を4カ所設けた。この代わりに、図4(A1)、図4(A2)、図4(A3)に示すように3カ所設けることも、また、図4(B1)、図4(B2)、図4(B3)に示すように5カ所以上設けることも可能である。
以下、本発明の第2実施形態に係る半導体搭載用リードピンを図5〜図7を参照して説明する。
図5(A)は、第2実施形態に係る半導体搭載用リードピンの平面図であり、図5(B)は側面であり、図5(C)は斜視図である。
半導体搭載用リードピン10は、円筒状の軸12と円形平板状の鍔20とからなる。鍔20は、パッケージ基板の電極パッドに当接可能な面状の平坦部22と、該平坦部22から凹んだ4つの溝部24とから成る。平坦部22は、鍔20と同心状の円部22Cと、該円部22Cから側端20E側へ延在し、上端(つら位置)が当該円部22Cと同じ高さになる断面半円状の延在部22Hとから構成されている。平坦部22は、軸12の中心CNと延在部22Hの最も高い部位とを通る垂線VLに対して対称に成るように形成されている。溝部24は側端20Eから中央側に向けて形成されている。
図5を参照して上述した第2実施形態の半導体搭載用リードピン10では、鍔20の溝部24を4カ所設けた。この代わりに、図4(A1)、図6(A2)、図6(A3)に示すように3カ所設けることも、また、図6(B1)、図6(B2)、図6(B3)に示すように5カ所以上設けることも可能である。
図5を参照して上述した第2実施形態、及び、図6を参照して上述した第2実施形態の第1改変例、第2改変例、第3改変例では、延在部22Hを断面半円状に形成した。これに対して、図7(A)、図7(B)、図7(C)に示すように、延在部22Hの最上部に線状の平坦面22Fを設けることも好適である。
以下、本発明の第3実施形態に係る半導体搭載用リードピンを図8及び図9を参照して説明する。
図8(A)は、第3実施形態に係る半導体搭載用リードピンの平面図であり、図8(B)は側面であり、図8(C)は斜視図である。
半導体搭載用リードピン10は、円筒状の軸12と円形平板状の鍔20とからなる。鍔20は、パッケージ基板の電極パッドに当接可能な面状の平坦部22と、該平坦部22からV字状に凹んだ4つの溝部24とから成る。平坦部22は、鍔の中心CNから側端20Eへ十字状に延在する線状の延在部22Lから成る。平坦部22は、軸12の中心CNと溝部24の最も深い部位とを通る垂線VLに対して対称に成るように形成されている。溝部24は側端20Eから中央側に向けて形成されている。
図8を参照して上述した第3実施形態の半導体搭載用リードピン10では、鍔20の溝部24を4カ所設けた。この代わりに、図9(A1)、図9(A2)、図9(A3)に示すように3カ所設けることも、また、図9(B1)、図9(B2)、図9(B3)に示すように5カ所以上設けることも可能である。
ここで、第1実施形態の半導体搭載用リードピンの溝部24の深さH1を変えて行った試験結果について説明する。ここでは、360本の半導体搭載用リードピンを備えるパッケージ基板の6個(psc)製造して、半導体搭載用リードピンの傾きの有無を調べた。 比較例としては、図10中に示す平坦な鍔20を備える半導体搭載用リードピンをパッケージ基板に取り付けた。ここで、ICチップを接続する半田バンプに融点230℃のPb−Sn−Sb半田を用い、半導体搭載用リードピンを固定する半田として236℃のPb82−Sn10−Sb8半田を用いた。
この結果を図11中の図表に示す。
ここで、平坦部の面積が50%、即ち、溝部が50%の際には、240℃で40秒経過した際に1個のパッケージ基板に於いて半導体搭載用リードピンの傾きが観察された。即ち、50%以下であれば効果があることが判明した。ここで、実相時のプロセスのマージンという観点から、30%以下に設定することが望ましいことが分かった。
12 軸
20 鍔
20C 中央部
20E 側端
22 平坦部
22C 円部
22L 延在部
24 溝部
22F 平坦面
40 パッケージ基板
42 パッド
44 半田バンプ
46 パッド
48−a半田ペースト
48−b 半田
50 ICチップ
52 パッド
Claims (6)
- 軸と鍔とから成るT型の半導体搭載用リードピンにおいて、
前記鍔が、被接続パッドに当接可能な面状の平坦部と、該平坦部から凹んだ3以上の溝部とから成り、
平坦部が鍔の中央位置から側端まで延在すると共に、前記軸の中心を通る所定の垂線に対して対称に成るように形成され、溝部が側端から中央側に向けて形成されていることを特徴とする半導体搭載用リードピン。 - 前記溝部が、略半円状に形成されていることを特徴とする請求項1の半導体搭載用リードピン。
- 前記平坦部が、鍔と同心状の円部と、該円部から側端側へ延在し、上端が当該円部と同じ高さとなる断面半円状の延在部とからなることを特徴とする請求項1の半導体搭載用リードピン。
- 前記平坦部が、鍔の中心から側端へ延在する線状の延在部からなり、前記溝部が、断面V字形状に成形されていることを特徴とする請求項1の半導体搭載用リードピン。
- 前記平坦部の面積を鍔中の5〜50%にしたことを特徴とする請求項1〜請求項4のいずれか1の半導体搭載用リードピン。
- 前記平坦部の面積を鍔中の10〜30%にしたことを特徴とする請求項1〜請求項4のいずれか1の半導体搭載用リードピン。
Priority Applications (14)
Application Number | Priority Date | Filing Date | Title |
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JP2004268521A JP4836425B2 (ja) | 2004-09-15 | 2004-09-15 | 半導体搭載用リードピン |
KR1020077004235A KR20070068345A (ko) | 2004-09-15 | 2005-08-30 | 반도체 탑재용 리드 핀 및 프린트 배선판 |
PCT/JP2005/015771 WO2006030634A1 (ja) | 2004-09-15 | 2005-08-30 | 半導体搭載用リードピン及びプリント配線板 |
EP05777107A EP1764833B1 (en) | 2004-09-15 | 2005-08-30 | Lead pin for mounting semiconductor and printed wiring board |
CNB200580031012XA CN100446235C (zh) | 2004-09-15 | 2005-08-30 | 半导体安装用引脚和印制电路板 |
KR1020087024949A KR20080098081A (ko) | 2004-09-15 | 2005-08-30 | 반도체 탑재용 리드 핀 및 프린트 배선판 |
KR1020097022836A KR100993151B1 (ko) | 2004-09-15 | 2005-08-30 | 반도체 탑재용 리드 핀 및 프린트 배선판 |
CN2008101809770A CN101414594B (zh) | 2004-09-15 | 2005-08-30 | 半导体安装用引脚和印制电路板 |
US11/572,334 US7723620B2 (en) | 2004-09-15 | 2005-08-30 | Lead pin for mounting semiconductor and printed wiring board |
CN2008101809766A CN101414593B (zh) | 2004-09-15 | 2005-08-30 | 半导体安装用引脚和印制电路板 |
TW094130688A TW200629507A (en) | 2004-09-15 | 2005-09-07 | Lead pin for mounting semiconductor and wiring board |
TW098133545A TW201007906A (en) | 2004-09-15 | 2005-09-07 | Lead pin for mounting semiconductor and printed wiring board |
TW099119550A TW201041101A (en) | 2004-09-15 | 2005-09-07 | Lead pin for mounting semiconductor and printed wiring board |
US12/725,546 US8426748B2 (en) | 2004-09-15 | 2010-03-17 | Lead pin for mounting semiconductor and printed wiring board |
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JP2004268521A JP4836425B2 (ja) | 2004-09-15 | 2004-09-15 | 半導体搭載用リードピン |
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JP2010197532A Division JP2010268016A (ja) | 2010-09-03 | 2010-09-03 | 半導体搭載用リードピン |
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US (2) | US7723620B2 (ja) |
EP (1) | EP1764833B1 (ja) |
JP (1) | JP4836425B2 (ja) |
KR (3) | KR20080098081A (ja) |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010141298A (ja) * | 2009-10-26 | 2010-06-24 | Shinko Electric Ind Co Ltd | リードピン付配線基板及びリードピン |
JP2010141348A (ja) * | 2010-02-04 | 2010-06-24 | Shinko Electric Ind Co Ltd | リードピン付配線基板及びリードピン |
US8153900B2 (en) | 2007-08-30 | 2012-04-10 | Shinko Electric Industries Co., Ltd. | Wiring substrate with lead pin and lead pin |
US8379402B2 (en) | 2008-12-10 | 2013-02-19 | Shinko Electric Industries Co., Ltd. | Wiring board having lead pin, and lead pin |
JP6068645B2 (ja) * | 2013-07-30 | 2017-01-25 | 京セラ株式会社 | 配線基板および電子装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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CN112601353A (zh) * | 2020-12-23 | 2021-04-02 | 新沂市承翔电子有限公司 | 一种电子元件引脚和电子元件 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60106375A (ja) * | 1983-11-10 | 1985-06-11 | Nichicon Capacitor Ltd | 瞬間大電流発生装置 |
JPS63157457A (ja) * | 1986-12-22 | 1988-06-30 | Tokuriki Honten Co Ltd | リ−ドピン |
JPS6430853A (en) * | 1987-07-03 | 1989-02-01 | Saab Scania Ab | Controller for main lamp circuit of automobile |
JPH09223529A (ja) * | 1995-12-15 | 1997-08-26 | Ibiden Co Ltd | 電子部品搭載用基板及びその製造方法 |
JPH1035638A (ja) * | 1996-07-29 | 1998-02-10 | Kishimoto Akira | 耐熱耐圧性に優れた自立容器 |
JP2001291815A (ja) * | 2000-04-06 | 2001-10-19 | Ibiden Co Ltd | プリント配線板用導体ピン、多層プリント配線板 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6430853U (ja) | 1987-08-20 | 1989-02-27 | ||
JPH07320800A (ja) * | 1994-05-18 | 1995-12-08 | Star Micronics Co Ltd | 端子及びその製造方法 |
TW546806B (en) | 1999-11-08 | 2003-08-11 | Siliconware Precision Industries Co Ltd | Semiconductor package with common lead frame and heat sink |
US6229207B1 (en) | 2000-01-13 | 2001-05-08 | Advanced Micro Devices, Inc. | Organic pin grid array flip chip carrier package |
JP3378550B2 (ja) * | 2000-02-03 | 2003-02-17 | 日本特殊陶業株式会社 | リードピン付き配線基板 |
US6623283B1 (en) | 2000-03-08 | 2003-09-23 | Autosplice, Inc. | Connector with base having channels to facilitate surface mount solder attachment |
JP3585806B2 (ja) | 2000-03-15 | 2004-11-04 | 日本特殊陶業株式会社 | ピン付き配線基板 |
TW457681B (en) | 2000-04-20 | 2001-10-01 | Advanced Semiconductor Eng | Chip packaging method |
TW520076U (en) | 2001-12-28 | 2003-02-01 | Amkor Technology Taiwan Ltd | Improved design of IC leadframe |
TW563232B (en) | 2002-08-23 | 2003-11-21 | Via Tech Inc | Chip scale package and method of fabricating the same |
TWI220778B (en) | 2003-07-31 | 2004-09-01 | Chipmos Technologies Inc | Stage of inner lead bond and manufacturing method of the same |
TWM242600U (en) | 2003-09-03 | 2004-09-01 | Jau-Wei Lin | Head cap structure for combination screw |
JP4836425B2 (ja) * | 2004-09-15 | 2011-12-14 | イビデン株式会社 | 半導体搭載用リードピン |
-
2004
- 2004-09-15 JP JP2004268521A patent/JP4836425B2/ja active Active
-
2005
- 2005-08-30 CN CN2008101809766A patent/CN101414593B/zh active Active
- 2005-08-30 CN CNB200580031012XA patent/CN100446235C/zh active Active
- 2005-08-30 KR KR1020087024949A patent/KR20080098081A/ko active Application Filing
- 2005-08-30 KR KR1020097022836A patent/KR100993151B1/ko active IP Right Grant
- 2005-08-30 CN CN2008101809770A patent/CN101414594B/zh active Active
- 2005-08-30 US US11/572,334 patent/US7723620B2/en active Active
- 2005-08-30 WO PCT/JP2005/015771 patent/WO2006030634A1/ja active Application Filing
- 2005-08-30 EP EP05777107A patent/EP1764833B1/en active Active
- 2005-08-30 KR KR1020077004235A patent/KR20070068345A/ko active Application Filing
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- 2005-09-07 TW TW099119550A patent/TW201041101A/zh unknown
-
2010
- 2010-03-17 US US12/725,546 patent/US8426748B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60106375A (ja) * | 1983-11-10 | 1985-06-11 | Nichicon Capacitor Ltd | 瞬間大電流発生装置 |
JPS63157457A (ja) * | 1986-12-22 | 1988-06-30 | Tokuriki Honten Co Ltd | リ−ドピン |
JPS6430853A (en) * | 1987-07-03 | 1989-02-01 | Saab Scania Ab | Controller for main lamp circuit of automobile |
JPH09223529A (ja) * | 1995-12-15 | 1997-08-26 | Ibiden Co Ltd | 電子部品搭載用基板及びその製造方法 |
JPH1035638A (ja) * | 1996-07-29 | 1998-02-10 | Kishimoto Akira | 耐熱耐圧性に優れた自立容器 |
JP2001291815A (ja) * | 2000-04-06 | 2001-10-19 | Ibiden Co Ltd | プリント配線板用導体ピン、多層プリント配線板 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8153900B2 (en) | 2007-08-30 | 2012-04-10 | Shinko Electric Industries Co., Ltd. | Wiring substrate with lead pin and lead pin |
US8379402B2 (en) | 2008-12-10 | 2013-02-19 | Shinko Electric Industries Co., Ltd. | Wiring board having lead pin, and lead pin |
JP2010141298A (ja) * | 2009-10-26 | 2010-06-24 | Shinko Electric Ind Co Ltd | リードピン付配線基板及びリードピン |
JP4606504B2 (ja) * | 2009-10-26 | 2011-01-05 | 新光電気工業株式会社 | リードピン付配線基板及びリードピン |
JP2010141348A (ja) * | 2010-02-04 | 2010-06-24 | Shinko Electric Ind Co Ltd | リードピン付配線基板及びリードピン |
JP6068645B2 (ja) * | 2013-07-30 | 2017-01-25 | 京セラ株式会社 | 配線基板および電子装置 |
JPWO2015016289A1 (ja) * | 2013-07-30 | 2017-03-02 | 京セラ株式会社 | 配線基板および電子装置 |
US9883589B2 (en) | 2013-07-30 | 2018-01-30 | Kyocera Corporation | Wiring board, and electronic device |
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US8426748B2 (en) | 2013-04-23 |
TW201041101A (en) | 2010-11-16 |
US20080055874A1 (en) | 2008-03-06 |
EP1764833B1 (en) | 2013-04-03 |
CN101414593A (zh) | 2009-04-22 |
CN100446235C (zh) | 2008-12-24 |
JP4836425B2 (ja) | 2011-12-14 |
CN101414593B (zh) | 2011-12-21 |
TWI331384B (ja) | 2010-10-01 |
US20100187004A1 (en) | 2010-07-29 |
EP1764833A1 (en) | 2007-03-21 |
KR20080098081A (ko) | 2008-11-06 |
KR20070068345A (ko) | 2007-06-29 |
CN101414594B (zh) | 2011-01-12 |
KR20090122310A (ko) | 2009-11-26 |
US7723620B2 (en) | 2010-05-25 |
EP1764833A4 (en) | 2009-09-23 |
CN101414594A (zh) | 2009-04-22 |
WO2006030634A1 (ja) | 2006-03-23 |
CN101019231A (zh) | 2007-08-15 |
KR100993151B1 (ko) | 2010-11-09 |
TW201007906A (en) | 2010-02-16 |
TW200629507A (en) | 2006-08-16 |
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Free format text: JAPANESE INTERMEDIATE CODE: R250 |