457681 五、發明說明（1) 本發明係有關一種晶片封裝方法，特別有關於一種使 引腳呈上寬下窄形狀之晶片封裝方法。 電子封裝（e 1 ectron ic packagi ng)製程一般係指將半 導體積體電路元件（semiconductor integrated circuit de v i ce )(在此指半導體晶粒或晶片）黏貼於一支撐基板 (supporting substrate)表面’並利用金屬打線（wire bonding)連接銲墊至基板表面’同時封入封膠材料 (mo ldi ng compound)以確保晶粒不受外界環境的污染。 但由於傳統封裝方式如雙列式封裝（D丨p : d ua 1 inline package)的封裝腳數（pin count)並不高，因 此’為大幅增加封裝腳數近來已發展出一種球格陣列封裝 其中’為了因應電子元件曰益輕薄短小之要求，更進而發 展出整個封裝體大小與晶片尺寸相去無幾（相差2〇%以内） 的晶片尺寸級封裝技術。 第1圖係為根據中華民國公告第348306號專利「具樹 脂封裝體之元件及其製造方法」一較佳實施例之低引腳數 半導體晶片封裝構造1〇 ’其包含一晶片11包覆於一封膠體 12内。該晶片11之正面具有複數個晶片銲墊電性連接 至複數個引腳1 3。該晶片11之背面係以一導電膠層14裸露 於該封膠體1 2。該複數個引腳1 3係環繞該晶片丨1而設並且 裸露於該封膠體12之下表面用以電性連接至外部。由於該 封膠體12並未包覆該複數個引腳13裸露之下表面，因此其 無法穩固地固定該複數個引腳丨3。457681 V. Description of the invention (1) The present invention relates to a chip packaging method, and more particularly to a chip packaging method for making pins into a wide shape and a narrow shape. The electronic packaging (e 1 ectron ic packagi ng) process generally refers to bonding a semiconductor integrated circuit element (herein, a semiconductor die or wafer) to a surface of a supporting substrate 'and Metal bonding is used to connect the bonding pads to the substrate surface, and at the same time, a mold compound is sealed to ensure that the die is not polluted by the external environment. However, due to the traditional package methods such as dual-line package (D 丨 p: d ua 1 inline package), the pin count of the package is not high. Therefore, a ball grid array package has recently been developed to greatly increase the number of package pins. Among them, in order to meet the requirements of light, thin, and short electronic components, it has further developed a chip-size packaging technology that has the same package size as the wafer size (with a difference of less than 20%). FIG. 1 is a low-pin-count semiconductor chip package structure 10 ′ according to a preferred embodiment of the “Resin-Packaged Component and Manufacturing Method” according to the Republic of China Publication No. 348306, which includes a wafer 11 coated on Inside a colloid 12. The front surface of the chip 11 has a plurality of chip pads electrically connected to the pins 13. The back surface of the wafer 11 is exposed to the encapsulant 12 with a conductive adhesive layer 14. The plurality of pins 13 are arranged around the chip 1 and exposed on the lower surface of the sealing compound 12 for electrical connection to the outside. Since the encapsulant 12 does not cover the exposed lower surface of the plurality of pins 13, it cannot securely fix the plurality of pins 3.
457681 五、發明說明（2) 此外’由於該封膠體丨2只密 來自空氣之濕氣及/或離子污染有、a曰片11之一邊，因此 大幅降低晶片運作壽命。冑著半1 y)問題’換S之， 置封裝於越來越小之封裝====將電子裳 有鑑於此，本發明之目的=見象也就越來越關鍵。 形成水氣入侵之途徑之問題 在於解決引腳容易脫落或 本發明提出一種晶片封裝方 提供-導電純，然後定義土 2列步：’首先 開口，其中開口頂部寬^形成複數個 於該些開口中，平坦化導電心矣接著填滿-絕緣材料 電基板形成複數個由絕緣材；開：底部，，導 基板使導電基板下表面朝:料其次反轉導電 刊工並黏貼一晶片於導雷篡柘下 表面二然，提供複數條導線以電性連接晶片至該些引腳， 以及始、封晶片及該些導線。 4描ΠΪί: 一種晶片封裝方法，包括下列步驟，首 先=-導電基板，其包括一晶片承載區及一鲜塾區’然 後疋義導電基板上表面以於銲墊區形成複數個開口其中 ^頂口底部’接著填滿—絕緣材料於該些開口 平*_化導電基板下表面至開口底部，使導電基板之銲 墊區形成複數個由絕緣材料隔離之引腳，其次反轉導電基 板使V電基板下表面朝上，並黏貼一晶片於導電基板下表 457681457681 V. Description of the invention (2) In addition, since the sealant 2 is densely contaminated by moisture and / or ions from the air, one side of the film 11 is greatly reduced, so the operating life of the chip is greatly reduced. Holding a half 1 y) question ’In other words, the package is placed in a smaller and smaller package ==== electronic clothes In view of this, the purpose of the present invention = seeing is becoming more and more critical. The problem of forming a path of water vapor invasion is to solve the problem that the pins are easy to fall off or the present invention proposes a chip package providing-conductive pure, and then defines the soil 2 steps: 'First open, where the top of the opening is wide ^ to form a plurality of these openings In the process, the conductive core is flattened and then filled with an insulating material. The electrical substrate is formed of a plurality of insulating materials. Open: at the bottom, the conductive substrate has the lower surface of the conductive substrate facing: it is expected that the conductive journal is reversed and a wafer is pasted to the mine The lower surface is tampered with, and a plurality of wires are provided to electrically connect the chip to the pins, and to start and seal the chip and the wires. 4 描 ΠΪί: A chip packaging method, including the following steps, first =-a conductive substrate, which includes a wafer carrying area and a fresh area 'then the upper surface of the conductive substrate is defined so as to form a plurality of openings in the pad area. The bottom of the mouth is then filled—the insulating material flattenes the bottom surface of the conductive substrate to the bottom of the opening, so that the pad area of the conductive substrate forms a plurality of pins separated by the insulating material, and then the conductive substrate is inverted to make V The lower surface of the electrical substrate is facing up, and a chip is pasted on the conductive substrate.
五、發明說明（3) 其中，由於填充絕緣材 得在反轉導電基板後，鄰接 狀’因而引腳不易脫落，也 片封裝之可靠度得以提升。 圖式簡單說明 料之開口的頂部寬於底部，使 絕緣材料之引腳呈上寬下窄形 不易形成水氣入侵路徑，故晶 為讓本發明之上述目的 懂，下文特舉一較佳實施例 明如下： 特徵、和優點能更明顯易 並配合所附圖式，作詳細說 第1圖係顯示一種BG A封裝之半導體積體電路元件。 第2A至2G圖顯示本發明之一實施例之製程剖面圖。 第2H圖顯示第2F圖之上視圖。 第3A至3G圖顯示本發明之一實施例之製程剖面圖。 第3H圖顯示第3F圖之上視圖。 [符號說明] 晶片封裝構造〜1 0 ;晶片〜11 ;封膠體〜j 2 ;晶片銲墊 〜11a ’引腳〜13 ;導電膠層〜14 ;基板〜、2〇〇 ;晶片 '140、240 ;導線〜150、250 ;封襞材料~16〇、26〇 ;引腳 ~100c、200c ;圖案化光阻層〜11〇、21〇 ;開口〜12〇、 220 ’絕緣材料〜130、230 ;銲塾區〜220’ ；晶片承載區 〜215’ ；開口頂部〜i2〇a、220a ;開口底部〜i20b、220b ; 基板上表面〜l〇〇b、200b ;基板下表面〜100c、2〇〇c 較佳實施例說明： 請參閱第2A至2G圖’其顯示本發明之一實施例之製程 剖面圖。V. Description of the invention (3) Among them, since the insulating material is filled so as to be adjacent after the conductive substrate is inverted, the pins are not easy to fall off, and the reliability of the chip package is improved. The figure briefly explains that the top of the opening of the material is wider than the bottom, so that the pins of the insulating material are wide and narrow, and it is not easy to form a water vapor invasion path. The examples are as follows: Features and advantages can be more obvious and easy to match with the attached drawings, the detailed description. Figure 1 shows a BG A packaged semiconductor integrated circuit element. Figures 2A to 2G show cross-sectional views of a manufacturing process according to an embodiment of the present invention. Figure 2H shows a top view of Figure 2F. Figures 3A to 3G show cross-sectional views of a manufacturing process according to an embodiment of the present invention. Figure 3H shows a top view of Figure 3F. [Symbol description] Chip package structure ~ 10; wafer ~ 11; sealing compound ~ j2; wafer pad ~ 11a 'pin ~ 13; conductive adhesive layer ~ 14; substrate ~~ 200; wafer'140, 240 Leads ~ 150, 250; Sealing materials ~ 16, 26; Pins ~ 100c, 200c; Patterned photoresist layer ~ 11, 21; Openings ~ 12, 220 'Insulating materials ~ 130, 230; Welding area ~ 220 '; Wafer loading area ~ 215'; Top of opening ~ i20a, 220a; Bottom of opening ~ i20b, 220b; Upper surface of substrate ~ 100b, 200b; Lower surface of substrate ~ 100c, 200 c Description of the preferred embodiment: Please refer to Figs. 2A to 2G ', which shows a cross-sectional view of a manufacturing process according to an embodiment of the present invention.
第7頁 457681 五、發明說明（4) 育先依據第2A圖，其步驟為提供-導電基板1(}〇，例 如是由金屬銅材料製成。其t + ^& , 再次之步驟為定義導電基板，例 如’塗佈-層光阻材料以覆蓋導電基板缺 後曝光及顯影該層光阻材料彡 阁安& , …、 « - ^ A Ba 何料以形成一圖案化光阻層110。 ㈣'2C圖’以圖案化光阻層11〇為罩 幕，利用濕餘刻或乾轴刻製程钱刻導電基板_ 數個開口 1 20，其中開口頂邱丨9n QW W银 τw τ貝邛I 2 0 a見於開口底部丨2 〇 b，例 如開口形狀係呈半圓形、二备來赤说犯黎 _ —再形或梯形4，然後如第2C圖 所不’除去圖案化光阻層丨丨〇 〇 其次，请參閱第2D圖，填滿一絕緣材料於該些開口 中，例如先預注入（pre-m〇lding) 一封膠材料13〇(㈣iding compound)如環氧化合物（ep〇xy)於導電基板1〇〇表面並填 滿該些開口，然後待封膠材料自然冷卻後，利用蝕刻或研 磨方式（grind)除去導電基板表面i〇〇a上多餘之封 Μ ΎΤ ° 請參閱第2Ε圖’利用蝕刻或研磨步驟以平坦化導電基 板下表面100b至開口底部120b，使導電基板1〇〇形成複數 個由絕緣材料130隔離之引腳iooc。 其次’請參閱第2F圖，反轉導電基板丨0〇使導電基板 下表面10 0b朝上’其上視圖如第2H圖所示，導電基板100 係全面性形成引腳1 〇 〇 c，故此種晶片封裝方式可具有較多 之引腳數目。 然後請參閱第2 G圖，黏貼一晶片1 4 〇於導電基板下表 面1 00b，其次提供複數條導線1 5〇以電性連接晶片1 4〇至該Page 7 457681 V. Description of the invention (4) According to Figure 2A, Yuxian's steps are to provide-conductive substrate 1 (} 〇, for example, made of metallic copper material. Its t + ^ &, the next step is Define a conductive substrate, such as' coated-layer photoresist material to cover the conductive substrate after exposure and develop the layer of photoresist material 彡 格安 &, ..., «-^ A Ba What to form a patterned photoresist layer 110. ㈣'2C 图 'uses patterned photoresist layer 11 as a mask, and uses a wet or dry-axis engraving process to etch conductive substrates _ several openings 1 20, of which the opening top Qiu 9n QW W silver τw τ Behr I 2 0 a is seen at the bottom of the opening 丨 2 〇b, for example, the shape of the opening is semi-circular, Er Beilai Chi said guilty _ — shape or trapezoid 4, and then the patterned light is not removed as shown in Figure 2C Resistive layer 丨 丨 〇〇 Second, please refer to FIG. 2D, fill an opening with an insulating material, for example, pre-mold an epoxy material 13〇 (㈣iding compound) such as an epoxy compound (Ep〇xy) on the surface of the conductive substrate 100 and fill the openings, and then after the sealant material is naturally cooled, use an etch Or grinding (grind) to remove the excess seal on the surface of the conductive substrate i 〇 ° ° See Figure 2E 'using the etching or polishing step to flatten the lower surface of the conductive substrate 100b to the bottom 120b of the opening, so that the conductive substrate 1〇 〇 form a plurality of pins iooc isolated by an insulating material 130. Secondly, 'see Figure 2F, invert the conductive substrate 丨 0 〇 make the lower surface of the conductive substrate 10 0b up', the top view is shown in Figure 2H, conductive The substrate 100 is completely formed with a pin 100c, so this chip packaging method can have a larger number of pins. Then refer to Figure 2G, and paste a wafer 1 40 on the lower surface of the conductive substrate 100b, followed by Provide a plurality of wires 150 to electrically connect the chip 140 to the
IHE 45768 1 五、發明說明（5) 些引腳100c，接著以封膠材料160密封晶片140及該些導線 1 5 0，然後實施硬化製程完成晶片封裝。 其中’如第2D圖所示，在預注入（pre-molding)封移 材料130後並不實施硬化製程（curing)，而是使封膠材料 1 3 0自然冷卻，藉此使其活性未完全發揮，如此，在進行 第2G圖之後續以封膠材料1 6 0密封晶片1 40之製程步騾時， 封膠材料160與後製程之封膠材料130之間的接觸介面可形 成較佳之結合，同時可節省一道硬化製程及所需之成本。 請參閱第3A至3G圖，其顯示本發明之另一實施例之製 程剖面圖。 首先依據第3A圖，其步驟為提供—導電基板2〇〇，例 如是由金屬銅材料製成。其次之步驟為定義導電基板，例 如’先塗佈一層光阻材料以覆蓋導電基板上表面20〇a，然 後曝光及顯影該層光阻材料以形成一圖案化光阻層21〇。 接著請參閱第3B、3C圖’以圖案化光阻層21〇為罩 幕’利用濕餘刻或乾蝕刻製程蝕刻導電基板2 〇 〇以於銲墊 區2 2 0形成複數個開口 2 2 0 ’其中開口頂部2 2 〇 a寬於開口 底部22 0b，例如開口形狀係呈半圓形、三角形或梯形等， 然後如第3C圖所示，除去圖案化光阻層2丨〇。 其次’清參閱第3D圖’填滿一絕緣材料2 3 〇於該些開 口 220中，例如先預注入一封膠材料如環氧化合物（ep〇xy ) 於導電基板表面20 〇a並填滿該些開口，然後待封膠材料自 然冷卻後，利用蝕刻或研磨方式（gr i nd)除去導電基板表 面200a上多餘之封膠材料。IHE 45768 1 V. Description of the invention (5) Some pins 100c, then the chip 140 and the wires 150 are sealed with a sealing material 160, and then a hardening process is performed to complete the chip package. Wherein, as shown in FIG. 2D, after the pre-molding of the sealing material 130, curing is not performed, but the sealing material 1 30 is naturally cooled, thereby making its activity incomplete. In this way, the contact interface between the sealant material 160 and the sealant material 130 in the subsequent process can form a better combination when the subsequent process steps of sealing the wafer 1 40 with the sealant material 160 in FIG. 2G are performed. At the same time, it can save a hardening process and the required costs. Please refer to FIGS. 3A to 3G, which are process cross-sectional views of another embodiment of the present invention. First, according to FIG. 3A, the step is to provide a conductive substrate 200, for example, made of a metallic copper material. The next step is to define a conductive substrate. For example, 'a layer of photoresist is applied to cover the upper surface of the conductive substrate 20a, and then the layer of photoresist is exposed and developed to form a patterned photoresist layer 21o. Next, please refer to FIGS. 3B and 3C. “Using the patterned photoresist layer 21〇 as a mask” uses a wet etching or dry etching process to etch the conductive substrate 2 to form a plurality of openings 2 2 0 in the pad area 2 2 0. 'Where the opening top 2 2a is wider than the opening bottom 22 0b. For example, the shape of the opening is semicircular, triangular, or trapezoidal, and then the patterned photoresist layer 2 is removed as shown in FIG. 3C. Secondly, "clearly refer to the 3D picture" is filled with an insulating material 2 3 0 in the openings 220, for example, a plastic material such as an epoxy compound (ep〇xy) is pre-injected on the surface of the conductive substrate 20 0a and filled. After these openings, after the sealant material is naturally cooled, the excess sealant material on the surface of the conductive substrate 200a is removed by etching or grinding.
第9頁 457681 五、發明說明（6) 請參閱第3 E圖’利用餘刻或研磨步驟以平坦化導電基 板下表面200b至開口底部220b ’使導電基板形成複數個由 絕緣材料230隔離之引腳2〇〇c。Page 9 457681 V. Description of the invention (6) Please refer to Figure 3E 'Using the remaining or grinding step to flatten the lower surface of the conductive substrate 200b to the bottom 220b' to make the conductive substrate form a plurality of leads separated by the insulating material 230 Feet 200c.
其次’請參閱第3F圖’反轉導電基板2〇〇使導電基板 下表面200b朝上，其上視圖如第311圖所示，導電基板2〇Q 係於銲墊區220’形成引腳2〇〇c，並預留一晶片承載區 215，。 然後請參閱第3G圖’黏貼一晶片240於導電基板下表 面200b之晶片承載區215，，其次提供複數條導線25〇以電 性連接晶片240至該些引腳2〇〇c，接著以封膠材料26〇密封 晶片240及該些導線2 5 0，然後實施硬化製程完成晶片 裝。 其中，如第3D圖所示，在預注入（pre_m〇iding)封膠 材料230後並不實施硬化製程（curing)，而是使封膠材^ 230自然冷卻，藉此使其活性未完全發揮’如此，在進行 第3G圖之後續以封膠材料26〇密封晶片24〇之製程步驟 封膠材料2 60與後製程之封膠材料23〇之間的接觸介面可 成較佳之結合，同時可節省一道硬化製程及所需之成本。 依據上述實施例可知，鄰接絕緣材料13〇、23〇之 100c、200c係呈上寬下窄形狀，因而引腳不易脫落， 易形成水氣入侵路徑，故晶片封裝之可靠度得以提升。 雖然本發明已以較佳實施例揭露如上，然其並非用 =疋本發明，任何熟習此項技藝者在不脫離本發明之 神和範圍β，當可作更動與潤飾，因此本發明之保護範：Next, please refer to FIG. 3F. Invert the conductive substrate 200 so that the lower surface 200b of the conductive substrate faces upward. The top view is shown in FIG. 311. The conductive substrate 20Q is tied to the pad area 220 'to form the lead 2. 〇c, and a wafer carrying area 215 is reserved. Then refer to FIG. 3G, “A wafer 240 is pasted to the wafer carrying area 215 of the lower surface 200b of the conductive substrate, and then a plurality of wires 25 are provided to electrically connect the wafer 240 to the pins 200c, and then sealed with The adhesive material 26 seals the wafer 240 and the wires 250, and then performs a hardening process to complete the wafer assembly. Among them, as shown in FIG. 3D, after the pre-molding sealing material 230 is pre-injected, the curing process is not performed, but the sealing material ^ 230 is naturally cooled, so that its activity is not fully exerted. 'In this way, the contact interface between the sealant material 2 60 and the sealant material 23 in the post-process can be better combined while the subsequent process steps of sealing the wafer 24 with the sealant material 26 and performing the subsequent step of FIG. 3G can be combined. Save a hardening process and required costs. According to the above embodiment, it can be known that the 100c and 200c adjacent to the insulating materials 13 and 23 have a wide width and a narrow shape, so the pins are not easy to fall off, and a water vapor intrusion path is easily formed, so the reliability of the chip package is improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to be used in the present invention. Any person skilled in the art can make changes and retouch without departing from the spirit and scope β of the present invention. Therefore, the protection of the present invention Fan:
第10頁 457681 五、發明說明¢7) 當視後附之申請專利範圍所界定者為準。 milPage 10 457681 V. Description of the invention ¢ 7) Subject to the scope of the attached patent application. mil