CN101019231A - 半导体安装用引脚和印制电路板 - Google Patents

半导体安装用引脚和印制电路板 Download PDF

Info

Publication number
CN101019231A
CN101019231A CNA200580031012XA CN200580031012A CN101019231A CN 101019231 A CN101019231 A CN 101019231A CN A200580031012X A CNA200580031012X A CN A200580031012XA CN 200580031012 A CN200580031012 A CN 200580031012A CN 101019231 A CN101019231 A CN 101019231A
Authority
CN
China
Prior art keywords
lead pin
mounting semiconductor
flange
par
slot part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA200580031012XA
Other languages
English (en)
Other versions
CN100446235C (zh
Inventor
川出雅德
郭贺宽之
虾名诚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
TIBC Co Ltd
Original Assignee
Ibiden Co Ltd
TIBC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd, TIBC Co Ltd filed Critical Ibiden Co Ltd
Publication of CN101019231A publication Critical patent/CN101019231A/zh
Application granted granted Critical
Publication of CN100446235C publication Critical patent/CN100446235C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1031—Surface mounted metallic connector elements
    • H05K2201/10318—Surface mounted metallic pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/1075—Shape details
    • H05K2201/1084—Notched leads
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

本发明提供一种在进行回流焊时不倾斜的半导体安装用引脚。如图3(A)所示，有时在电极焊盘(44)与半导体安装用引脚的凸缘(20)之间的焊锡(48)内残留有空穴(B)。当为了安装IC芯片而进行回流焊时，连接用的焊锡(48)侧也熔化，并且焊锡内的空穴(B)膨胀。如图3(B)所示，由于空穴沿着槽部(24)向侧面排出，所以凸缘(20)被空穴(B)抬起，从而半导体安装用引脚(10)不会倾斜。

Description

半导体安装用引脚和印制电路板
技术领域
本发明涉及用于半导体封装与基板侧插座的连接的半导体安装用引脚。
背景技术
为了应对近年来的高布线密度化，PGA(针栅阵列)式半导体封装基板中的引脚，通常是由使用插入封装基板侧的通孔的插入型引脚，使用用焊锡连接于封装基板的焊盘上的T型引脚。
T型引脚由焊锡固定于封装基板的电极焊盘上，同样，IC芯片也由焊锡固定于封装基板的电极焊盘上。在此，通过改变铅的含量，或改变金属组成，来使T针连接用焊锡与IC芯片连接用焊锡的熔点不同，从而在通过回流焊连接IC芯片时，固定半导体安装用引脚的焊锡不熔化。
在专利文献1中公开了用于提高T型针的抗拉强度的技术。
专利文献1：日本特开2001-267451号公报
近年来，考虑到对环境的影响，而使用不含铅的焊锡(例如，锡-银-铜焊锡，锡-锑焊锡)，焊锡的熔点提高。因此，在通过回流焊熔化焊锡块而将IC芯片安装于封装基板上时，半导体安装用引脚连接用的焊锡熔化而半导体安装用引脚倾斜，发生无法向子插件侧插座安装这样的问题。现在，在CPU用封装基板上安装着几百根半导体安装用引脚，但即使其中有-根倾斜，则CPU就成为无法安装到插座的不良品。
参照图10(A)、图10(B)和图3(C)、图3(D)进一步说明该半导体安装用引脚的倾斜。
图10(A)示出封装基板40。在封装基板40的上表面的电极焊盘42上形成有焊锡块46，在下表面侧的电极焊盘44上通过焊锡48安装有半导体安装用引脚10。在此，如图10(B)中所示，在通过回流焊熔化封装基板40上表面的焊锡块46而使其连接于IC芯片50的电极焊盘52来安装IC芯片50时，存在半导体安装用引脚10倾斜的情况。
图3(C)示出图10(A)中的椭圆C内的半导体安装用引脚10，图3(D)示出图10(B)中的椭圆C内的半导体安装用引脚10。如图10(B)所示，在半导体安装用引脚10倾斜时，如图3(C)所示，得知在电极焊盘44与半导体安装用引脚10的凸缘20之间的焊锡48内残留有空穴B。并且，在如上述那样为了安装IC芯片50而进行回流焊时，明显得知如图3(D)所示，连接用焊锡48也熔化，并且焊锡内的空穴B膨胀，凸缘20被该空穴抬起(向下推)，半导体安装用引脚10倾斜。
发明内容
本发明是为了解决上述课题而作成的，其目的在于提供一种在进行回流焊时不会倾斜的半导体安装用引脚。
为了实现上述目的，技术方案1的发明，在由轴杆与凸缘构成的半导体安装用引脚中，其特征在于，
上述凸缘由能够与被连接焊盘抵接的面状的平坦部、和从该平坦部凹陷的三个以上的槽部组成，
平坦部形成为从凸缘的中央位置延伸到侧端，并相对于通过上述轴杆的中心的规定的垂线对称，槽部从侧端向中央侧形成。
在技术方案1的半导体安装用引脚中，凸缘由能够与被连接焊盘抵接的面状的平坦部、和从该平坦部凹陷的三个以上的槽部组成，平坦部从凸缘的中央位置延伸到侧端，槽部从侧端向中央侧形成。即，由于在凸缘上从侧端向中央侧形成槽部，所以在被连接焊盘与凸缘之间的焊锡内残留空穴，在进行回流焊时即使空穴膨胀，也会沿着槽部向侧方排出，从而凸缘因空穴而被抬起，半导体安装用引脚不会倾斜。进而，由于平坦部构成为从凸缘的中央位置延伸到侧端，并相对于通过轴杆的中心的规定垂线对称，所以可保持相对于封装基板的垂直性。
在技术方案2的半导体安装用引脚中，槽部形成为大致半圆形。由于是槽部向凸缘的侧端倾斜的结构，所以在进行回流焊时膨胀的空穴容易沿着槽部向侧方排出。
在技术方案3的半导体安装用引脚中，平坦部由与凸缘同心状的圆部、和半圆形截面的延伸部构成，该延伸部从该圆部延伸到侧端侧，其上端与该圆部相同高度。因此，用金属模可以容易成形平坦部。
在技术方案4的半导体安装用引脚中，槽部形成为V字形截面。由于是槽部向凸缘的侧端倾斜的结构，所以在进行回流焊时膨胀的空穴容易沿着槽部向侧方排出。
在技术方案5中，通过使平坦部的面积为凸缘的与轴杆垂直方向的截面积的5％以上，可以牢固地将该平坦部连接于被连接焊盘。另一方面，通过使平坦部的面积为凸缘的与轴杆垂直方向的截面积的50％以下，在进行回流焊时膨胀的空穴容易沿着槽部向侧方排出。
在技术方案6中，通过把平坦部的面积做成凸缘的与轴杆垂直方向的截面积的10％以上，可以牢固地将该平坦部连接于被连接焊盘。另一方面，通过使平坦部的面积为凸缘的与轴杆垂直方向的截面积的30％以下，在进行回流焊时膨胀的空穴容易沿着槽部向侧方排出。
在技术方案7的印制电路板中，半导体安装用引脚不会倾斜。
附图说明
图1(A)是本发明的第1实施方式的半导体安装用引脚的俯视图，图1(B)是侧视图，图1(C)是立体图。
图2是示出将半导体安装用引脚安装到封装基板上、以及安装IC芯片的工序的工序图。
图3(A)示出图2(B)中的椭圆C内的半导体安装用引脚10，图3(B)示出图2(C)中的椭圆C内的半导体安装用引脚10。图3(C)示出图10(A)中的椭圆C内的半导体安装用引脚10，图3(D)示出图10(B)中的椭圆C内的半导体安装用引脚10。
图4(A1)是第1实施方式的第1变型例的半导体安装用引脚的俯视图，图4(A2)是侧视图，图4(A3)是立体图。图4(B1)是第1实施方式的第2变型例的半导体安装用引脚的俯视图，图4(B2)是侧视图，图4(B3)是立体图。
图5(A)是第2实施方式的半导体安装用引脚的俯视图，图5(B)是例视图，图5(C)是立体图。
图6(A1)是第2实施方式的第1变型例的半导体安装用引脚的俯视图，图6(A2)是侧视图，图6(A3)是立体图。图6(B1)是第2实施方式的第2变型例的半导体安装用引脚的俯视图，图6(B2)是侧视图，图6(B3)是立体图。
图7(A)是第2实施方式的第3变型例的半导体安装用引脚的立体图，图7(B)是第4变型例的半导体安装用引脚的立体图，图7(C)是第6变型例的半导体安装用引脚的立体图。
图8(A)是第3实施方式的半导体安装用引脚的俯视图，图8(B)是侧视图，图8(C)是立体图。
图9(A1)是第3实施方式的第1变型例的半导体安装用引脚的俯视图，图9(A2)是侧视图，图9(A3)是立体图。图9(B1)是第3实施方式的第2变型例的半导体安装用引脚的俯视图，图9(B2)是侧视图，图9(B3)是立体图。
图10是表示将IC芯片安装到使用现有技术的半导体安装用引脚的封装基板上的安装工序的工序图。
图11是表示对平坦部的面积与凸缘的与轴杆垂直方向的截面积之比进行试验的结果的图表。
附图标记的说明：
10：半导体安装用引脚；12：轴杆；20：凸缘；20C：中央部；20E：侧端；22：平坦部；22C：圆部；22L：延伸部；24：槽部；22F：平坦面；40：封装基板；42：焊盘；44：焊锡块；46：焊盘；48-a：焊锡膏；48-b：焊锡；50：IC芯片；52：焊盘。
具体实施方式
〔第1实施方式〕
下面，参照图1～图4说明本发明的第1实施方式的半导体安装用引脚。
图1(A)是本发明的第1实施方式的半导体安装用引脚的俯视图，图1(B)是侧视图，图1(C)是立体图。
半导体安装用引脚10由圆柱状的轴杆12与凸缘20组成。凸缘20由能够与封装基板的电极焊盘抵接的面状的平坦部22、和从该平坦部22呈大致半圆状凹陷的四个槽部24构成。平坦部22被形成为从凸缘20的中央位置延伸到侧端20E，且相对于通过轴杆12的中心CN和槽部24的最深的部位的垂线VL对称。槽部24从侧端20E向中央侧地形成。
在此，半导体安装用引脚由铜合金等制造，总长L1形成为3.16mm。轴杆12的直径Φ2形成为0.45mm。凸缘20的直径Φ1形成为1.1mm，厚度T1形成为0.26mm。槽部24在最深的侧端20E处的深度H1形成为0.13mm。如图1(A)中所示，相对置的槽部24之间的间隔W1设定为0.45mm。
接下来，参照图2和图3说明将第1实施方式的半导体安装用引脚安装到封装基板上。
图2是表示将半导体安装用引脚安装到封装基板上、以及安装IC芯片的工序的工序图。如图2(A)所示，在封装基板40的上表面的电极焊盘42上形成有焊锡块46，在下表面侧的电极焊盘44上配置有连接用的焊锡膏48-a。在此，如图2(B)所示，通过回流焊熔化焊锡膏48-a，将半导体安装用引脚10安装到封装基板的下表面上。然后，如图2(C)所示，通过回流焊熔化封装基板40的上表面的焊锡块46而使其与IC芯片50的电极焊盘52连接。
图3(A)示出图2(B)中的椭圆C内的半导体安装用引脚10，图3(B)示出图2(C)中的椭圆C内的半导体安装用引脚10。如图3(A)所示，在焊锡块44与半导体安装用引脚的凸缘20之间的焊锡48-b内残留空穴B。如上述那样为了安装IC芯片而进行回流焊时，虽然连接用的焊锡48-b也熔化，并且焊锡内的空穴B膨胀，但由于该空穴B沿着图3(B)所示的槽部24向侧方排出，不会产生由于凸缘20因空穴B被抬起而导致半导体安装用引脚10倾斜的现象。
此外，在第1实施方式的半导体安装用引脚10中，槽部24形成为大致半圆形，是向凸缘20的侧端20E倾斜的结构，所以在进行回流焊时膨胀的空穴容易沿着槽部24向侧方排出。而且，即使空穴未从焊锡48-b排出，通过沿着槽部24张展，半导体安装用引脚10也不会倾斜。
另外，由于平坦部22被构成为从凸缘20的中央位置延伸到侧端20E，且相对于通过轴杆12的中心的垂线VL对称，所以即使在安装IC芯片的回流焊时连接用的焊锡48熔化了，半导体安装用引脚10也能保持相对于封装基板40的垂直性。
通过使用第1实施方式的半导体安装用引脚，即使不增大构成IC芯片连接用焊锡块46的焊锡与半导体安装用引脚连接用的焊锡48-b之间的熔点之差，也可以防止IC芯片回流焊时的半导体安装用引脚的倾斜。
图4(A1)是第1实施方式的第1变型例的半导体安装用引脚的俯视图，图4(A2)是侧视图，图4(A3)是立体图。图4(B1)是第1实施方式的第2变型例的半导体安装用引脚的俯视图，图4(B2)是侧视图，图4(B3)是立体图。
在参照图1说明的上述第1实施方式的半导体安装用引脚10中，设置四处凸缘20的槽部24。如图4(A1)、图4(A2)、图4(A3)所示，也可以设置三处来取代设置四处槽部24，此外，如图4(B1)、图4(B2)、图4(B3)所示，还可以设置五处以上来取代设置四处槽部24。
〔第2实施方式〕
下面，参照图5～图7说明本发明的第2实施方式的半导体安装用引脚。
图5(A)是第2实施方式的半导体安装用引脚的俯视图，图5(B)是侧视图，图5(C)是立体图。
半导体安装用引脚10由圆柱状的轴杆12与凸缘20构成。凸缘20由能够与封装基板的电极焊盘抵接的面状的平坦部22、和从该平坦部22凹陷的四个槽部24构成。平坦部22由与凸缘20同心状的圆部22C、和延伸部22H构成，该延伸部22H为半圆形截面，从该圆部22C延伸到侧端20E侧，上端(顶面位置)与该圆部22C相同高度。平坦部22形成为相对于通过轴杆12的中心CN和延伸部22H的最高部位的垂线VL对称。槽部24从侧端20E向中央侧形成。
在此，半导体安装用引脚由铜合金等制造，总长L1形成为3.16mm。轴杆12的直径Φ2形成为0.45mm。凸缘20的直径Φ1形成为1.1mm，厚度T1形成为0.26mm。槽部24的深度H1形成为0.05mm。如图1(A)所示，圆部22C的上端直径W3形成为0.45mm，下端直径W2形成为0.55mm。延伸部22H的宽度W4设定为0.2mm。
第2实施方式的半导体安装用引脚10，与第1实施方式同样，在为了安装IC芯片而进行回流焊时，由于在焊锡中膨胀的空穴B沿着槽部24向侧方排出，所以不会产生由于凸缘20因空穴B被抬起而导致半导体安装用引脚10倾斜的现象。
此外，在第2实施方式的半导体安装用引脚10中，平坦部22由与凸缘20同心状的圆部22C、和延伸部22H构成，该延伸部22H为半圆形截面，从该圆部22C延伸到侧端侧，上端与该圆部22C相同高度。因此，可容易用金属模具形成平坦部22。
而且，由于平坦部22被构成为其延伸部22H从凸缘20的中央位置延伸到侧端20E，并且相对于通过轴杆12的中心的垂线VL对称，所以在为了安装IC芯片而进行回流焊时，即使连接用的焊锡膏48-a熔化，半导体安装用引脚10也能保持相对于封装基板40的垂直性。
图6(A1)是第2实施方式的第1变型例的半导体安装用引脚的俯视图，图6(A2)是侧视图，图6(A3)是立体图。图6(B1)是第2实施方式的第2变型例的半导体安装用引脚的俯视图，图6(B2)是侧视图，图6(B3)是立体图。
在参照图5说明的上述第2实施方式的半导体安装用引脚10中，设有四处凸缘20的槽部24。如图6(A1)、图6(A2)、图6(A3)所示，可以设置三处来取代设置四处槽部24，此外，如图6(B1)、图6(B2)、图6(B3)所示，还可以设置五处以上来取代设置四处槽部24。
图7(A)是第2实施方式的第3变型例的半导体安装用引脚的立体图，图7(B)是第4变型例的半导体安装用引脚的立体图，图7(C)是第6变型例的半导体安装用引脚的立体图。
在参照图5说明的上述第2实施方式、及参照图6说明的上述第2实施方式的第1变型例、第2变型例、第3变型例中，将延伸部22H形成为半圆形截面。对此，如图7(A)、图7(B)、图7(C)所示，也可以在延伸部22H的最上表面设置线状的平坦面22F。
〔第3实施方式〕
下面，参照图8和图9说明本发明的第3实施方式的半导体安装用引脚。
图8(A)是第3实施方式的半导体安装用引脚的俯视图，图8(B)是侧视图，图8(C)是立体图。
半导体安装用引脚10由圆柱状的轴杆12与凸缘20构成。凸缘20由能够与封装基板的电极焊盘抵接的面状的平坦部22、和从该平坦部22呈V字形地凹陷的四个槽部24构成。平坦部22由从凸缘的中心CN呈十字形地延伸到侧端20E的线状的延伸部22L构成。平坦部22形成为相对于通过轴杆12的中心CN与槽部24的最深部位的垂线VL对称。槽部24从侧端20E向中央侧形成。
在此，半导体安装用引脚由铜合金等制造，总长L1形成为3.16mm。轴杆12的直径Φ2形成为0.46mm。凸缘20的直径Φ1形成为1.1mm，厚度T1形成为0.26mm。槽部24在最深的侧端20E处深度H2形成为0.13mm。如图1(A)所示，线状的延伸部22L的宽度W5设定为0.05mm。
第3实施方式的半导体安装用引脚10，与第1实施方式同样，在为了安装IC芯片而进行回流焊时，由于在焊锡内膨胀的空穴沿着槽部24向侧方排出，从而不会产生由于凸缘20因空穴B而被抬起而导致半导体安装用引脚10倾斜的现象。
此外，在第3实施方式的半导体安装用引脚10中，由于槽部24是形成为大致V字形、向凸缘20的侧端20E倾斜的结构，所以在进行回流焊时膨胀的空穴容易沿着槽部24向侧方排出。而且，即使空穴未从焊锡48排出，也会沿着槽部24扩展，从而半导体安装用引脚10不会倾斜。
而且，由于平坦部22形成为从凸缘20的中央位置延伸到侧端20E，且相对于通过轴杆12的中心的垂线VL对称，所以在为了安装IC芯片而进行回流焊时，即使连接用的焊锡48熔化了，半导体安装用引脚10也能保持相对于封装基板40的垂直性。
图9(A1)是第3实施方式的第1变型例的半导体安装用引脚的俯视图，图9(A2)是侧视图，图9(A3)是立体图。图9(B1)是第3实施方式的第2变型例的半导体安装用引脚的俯视图，图9(B2)是侧视图，图9(B3)是立体图。
在参照图8说明的上述第3实施方式的半导体安装用引脚10中，设置四处凸缘20的槽部24。如图9(A1)、图9(A2)、图9(A3)所示，可以设置三处槽部24来取代设置四处槽部24，此外，如图9(B1)、图9(B2)、图9(B3)所示，还可以设置五处以上槽部24来代替设置四处槽部24。
〔评价试验〕
在此，对改变第1实施方式的半导体安装用引脚的槽部24的深度H1而进行的试验结果进行说明。在此，制造六个(件)具有360根半导体安装用引脚的封装基板，调查半导体安装用引脚的倾斜的有无。作为比较例，把图10所示的具有平坦的凸缘20的半导体安装用引脚安装到封装基板上。在此，在连接IC芯片的焊锡块中使用熔点为230℃的Pb-Sn-Sb焊锡，作为固定半导体安装用引脚的焊锡使用236℃的Pb82-Sn10-Sb8焊锡。
在此，在把深度H1设定成0.04mm时，与使用现有技术的半导体安装用引脚的比较例同样，在六个封装基板中，在两个封装基板中观察到半导体安装用引脚的倾斜。在把深度H1设定为0.05mm时，不发生半导体安装用引脚的倾斜。由结果得知，最好是把深度H1设定成0.05mm以上。
相反，在把深度设定成2.1mm时，在一个封装基板中观察到半导体安装用引脚的倾斜。在把深度H1设定成2mm时，不发生半导体安装用引脚的倾斜。由该结果得知，最好是把深度H1设定成2mm以下。
而且，对平坦部的面积与凸缘的与轴杆垂直方向的截面积之比进行了试验。
将该结果示于图11中的图表。
在此，在平坦部的面积为50％，即、槽部为50％时，在240℃下经过了40秒时在一个封装基板中观察到半导体安装用引脚的倾斜。即，可知如果是平坦部的面积为50％以下则有效。在此，可知从安装时的处理的余量方面考虑，最好是平坦部设定为面积为30％以下。
相反，在把平坦部的面积做成4％时，不能得到规定的抗拉强度(4.5Kgf)，在做成5％时，能得到规定的抗拉强度。在此，即使做成10％以上，抗拉强度也不提高。由结果可知，通过把平坦部的面积做成5％以上，可以牢固地将该平坦部连接于被连接焊盘。
另外，在此所说的抗拉强度的测定方法，与日本特开2001-267451号公报的接合强度测定方法相同。
另外，虽然对第1实施方式的半导体安装用引脚进行了评价试验，但可以认为上述结果，在第2实施方式的半导体安装用引脚、第3实施方式的半导体安装用引脚中也可以得到同样的结果。
产业上的可利用性
在上述第1～第3实施方式中，对特定形状的平坦部和槽部进行了说明，当然是只要是通过设置槽部使空穴可以向侧方排出，就可以使用各种形状的平坦部和槽部。

Claims (7)

1.一种半导体安装用引脚，由轴杆与凸缘构成，其特征在于，其中，
上述凸缘由能够与被连接焊盘抵接的面状的平坦部、和从该平坦部凹陷的三个以上的槽部构成，
平坦部被形成为从凸缘的中央位置延伸到侧端，并相对于通过上述轴杆的中心的规定垂线对称，槽部从侧端向中央侧地形成。
2.根据权利要求1所述的半导体安装用引脚，其特征在于，上述槽部形成为大致半圆形。
3.根据权利要求1所述的半导体安装用引脚，其特征在于，上述平坦部由与凸缘同心状的圆部、和半圆形截面的延伸部构成，该延伸部从该圆部延伸到侧端侧，其上端与该圆部相同高度。
4.根据权利要求1所述的半导体安装用引脚，其特征在于，上述平坦部由从凸缘的中心延伸到侧端的线状的延伸部构成，上述槽部形成为V字形截面。
5.根据权利要求1～4中任一项所述的半导体安装用引脚，其特征在于，上述平坦部的面积为凸缘中没有槽的部分与轴杆垂直方向的截面积的5～50％。
6.根据权利要求1～4中任一项所述的半导体安装用引脚，其特征在于，上述平坦部的面积为凸缘中没有槽的部分与轴杆垂直方向的截面积的10～30％。
7.一种印制电路板，其特征在于，具有权利要求1～6中任一项所述的半导体安装用引脚。
CNB200580031012XA 2004-09-15 2005-08-30 半导体安装用引脚和印制电路板 Active CN100446235C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004268521A JP4836425B2 (ja) 2004-09-15 2004-09-15 半導体搭載用リードピン
JP268521/2004 2004-09-15

Related Child Applications (2)

Application Number Title Priority Date Filing Date
CN2008101809766A Division CN101414593B (zh) 2004-09-15 2005-08-30 半导体安装用引脚和印制电路板
CN2008101809770A Division CN101414594B (zh) 2004-09-15 2005-08-30 半导体安装用引脚和印制电路板

Publications (2)

Publication Number Publication Date
CN101019231A true CN101019231A (zh) 2007-08-15
CN100446235C CN100446235C (zh) 2008-12-24

Family

ID=36059889

Family Applications (3)

Application Number Title Priority Date Filing Date
CNB200580031012XA Active CN100446235C (zh) 2004-09-15 2005-08-30 半导体安装用引脚和印制电路板
CN2008101809770A Active CN101414594B (zh) 2004-09-15 2005-08-30 半导体安装用引脚和印制电路板
CN2008101809766A Active CN101414593B (zh) 2004-09-15 2005-08-30 半导体安装用引脚和印制电路板

Family Applications After (2)

Application Number Title Priority Date Filing Date
CN2008101809770A Active CN101414594B (zh) 2004-09-15 2005-08-30 半导体安装用引脚和印制电路板
CN2008101809766A Active CN101414593B (zh) 2004-09-15 2005-08-30 半导体安装用引脚和印制电路板

Country Status (7)

Country Link
US (2) US7723620B2 (zh)
EP (1) EP1764833B1 (zh)
JP (1) JP4836425B2 (zh)
KR (3) KR20080098081A (zh)
CN (3) CN100446235C (zh)
TW (3) TW200629507A (zh)
WO (1) WO2006030634A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103050456A (zh) * 2011-10-14 2013-04-17 南亚电路板股份有限公司 半导体装置承载引脚
CN108645521A (zh) * 2018-05-09 2018-10-12 东莞传晟光电有限公司 一种热释电传感器
CN109683396A (zh) * 2019-01-30 2019-04-26 厦门天马微电子有限公司 背光模组、显示面板、显示装置及背光模组的制作方法
CN112601353A (zh) * 2020-12-23 2021-04-02 新沂市承翔电子有限公司 一种电子元件引脚和电子元件

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4836425B2 (ja) * 2004-09-15 2011-12-14 イビデン株式会社 半導体搭載用リードピン
JP2009043844A (ja) * 2007-08-07 2009-02-26 Shinko Electric Ind Co Ltd リードピン付き配線基板およびリードピン
US8153900B2 (en) 2007-08-30 2012-04-10 Shinko Electric Industries Co., Ltd. Wiring substrate with lead pin and lead pin
DE102008005547B4 (de) * 2008-01-23 2013-08-29 Infineon Technologies Ag Leistungshalbleitermodul und Schaltungsanordnung mit einem Leistungshalbleitermodul
DE102008015378A1 (de) * 2008-03-20 2009-09-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Anschlussstift und elektrischer Anschluss
KR101003684B1 (ko) 2008-07-03 2010-12-23 삼성전기주식회사 패키지 기판용 리드핀
JP4613237B2 (ja) 2008-12-10 2011-01-12 新光電気工業株式会社 リードピン付配線基板及びリードピン
KR100959865B1 (ko) * 2009-07-20 2010-05-27 삼성전기주식회사 패키지 기판용 리드핀
KR100959866B1 (ko) * 2009-07-20 2010-05-27 삼성전기주식회사 패키지 기판용 리드핀
US8766450B2 (en) 2009-09-22 2014-07-01 Samsung Electro-Mechanics Co., Ltd. Lead pin for package substrate
JP4606504B2 (ja) * 2009-10-26 2011-01-05 新光電気工業株式会社 リードピン付配線基板及びリードピン
JP5396646B2 (ja) * 2010-02-04 2014-01-22 新光電気工業株式会社 リードピン付配線基板及びリードピン
US8529081B2 (en) 2010-04-23 2013-09-10 Surefire, Llc Headlamp device with housing providing thermal management
US8395058B2 (en) * 2010-04-23 2013-03-12 Surefire, Llc Metal core circuit board with conductive pins
KR20120017606A (ko) 2010-08-19 2012-02-29 삼성전기주식회사 패키지 기판용 리드핀 및 이를 이용한 패키지 기판의 제조 방법
KR101167443B1 (ko) * 2010-11-17 2012-07-19 삼성전기주식회사 인쇄회로기판용 리드핀과 이를 이용한 인쇄회로기판
KR101210093B1 (ko) * 2010-12-01 2012-12-07 삼성에스디아이 주식회사 연결탭 및 이를 구비한 이차전지
JP2012164965A (ja) * 2011-01-21 2012-08-30 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
TWI436529B (zh) * 2011-07-14 2014-05-01 Nan Ya Printed Circuit Board 電子元件
US8587019B2 (en) 2011-10-11 2013-11-19 Ledengin, Inc. Grooved plate for improved solder bonding
DE102011087616A1 (de) * 2011-12-02 2013-06-06 Robert Bosch Gmbh Kontaktstift
EP3030060B1 (en) 2013-07-30 2020-01-08 Kyocera Corporation Wiring base plate and electronic device
JP6481527B2 (ja) * 2015-06-25 2019-03-13 富士電機株式会社 半導体装置
CN106332449B (zh) * 2016-08-31 2019-03-05 安徽赛福电子有限公司 一种电子元件引脚

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60106375A (ja) * 1983-11-10 1985-06-11 Nichicon Capacitor Ltd 瞬間大電流発生装置
JPS63157457A (ja) * 1986-12-22 1988-06-30 Tokuriki Honten Co Ltd リ−ドピン
SE460279B (sv) * 1987-07-03 1989-09-25 Saab Scania Ab Styrdon foer en huvudljuskrets paa ett motorfordon
JPS6430853U (zh) 1987-08-20 1989-02-27
JPH07320800A (ja) * 1994-05-18 1995-12-08 Star Micronics Co Ltd 端子及びその製造方法
JP3843514B2 (ja) * 1995-12-15 2006-11-08 イビデン株式会社 電子部品搭載用基板及びその製造方法
JP3684692B2 (ja) * 1996-07-29 2005-08-17 東洋製罐株式会社 耐熱耐圧性に優れた自立容器
TW546806B (en) 1999-11-08 2003-08-11 Siliconware Precision Industries Co Ltd Semiconductor package with common lead frame and heat sink
US6229207B1 (en) 2000-01-13 2001-05-08 Advanced Micro Devices, Inc. Organic pin grid array flip chip carrier package
JP3378550B2 (ja) 2000-02-03 2003-02-17 日本特殊陶業株式会社 リードピン付き配線基板
US6623283B1 (en) 2000-03-08 2003-09-23 Autosplice, Inc. Connector with base having channels to facilitate surface mount solder attachment
JP3585806B2 (ja) 2000-03-15 2004-11-04 日本特殊陶業株式会社 ピン付き配線基板
JP4343390B2 (ja) * 2000-04-06 2009-10-14 イビデン株式会社 プリント配線板用導体ピン、多層プリント配線板
TW457681B (en) 2000-04-20 2001-10-01 Advanced Semiconductor Eng Chip packaging method
TW520076U (en) 2001-12-28 2003-02-01 Amkor Technology Taiwan Ltd Improved design of IC leadframe
TW563232B (en) 2002-08-23 2003-11-21 Via Tech Inc Chip scale package and method of fabricating the same
TWI220778B (en) 2003-07-31 2004-09-01 Chipmos Technologies Inc Stage of inner lead bond and manufacturing method of the same
TWM242600U (en) 2003-09-03 2004-09-01 Jau-Wei Lin Head cap structure for combination screw
JP4836425B2 (ja) * 2004-09-15 2011-12-14 イビデン株式会社 半導体搭載用リードピン

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103050456A (zh) * 2011-10-14 2013-04-17 南亚电路板股份有限公司 半导体装置承载引脚
CN108645521A (zh) * 2018-05-09 2018-10-12 东莞传晟光电有限公司 一种热释电传感器
CN109683396A (zh) * 2019-01-30 2019-04-26 厦门天马微电子有限公司 背光模组、显示面板、显示装置及背光模组的制作方法
CN112601353A (zh) * 2020-12-23 2021-04-02 新沂市承翔电子有限公司 一种电子元件引脚和电子元件

Also Published As

Publication number Publication date
KR20080098081A (ko) 2008-11-06
US20100187004A1 (en) 2010-07-29
TW200629507A (en) 2006-08-16
EP1764833B1 (en) 2013-04-03
EP1764833A4 (en) 2009-09-23
US8426748B2 (en) 2013-04-23
KR20090122310A (ko) 2009-11-26
CN101414593A (zh) 2009-04-22
EP1764833A1 (en) 2007-03-21
CN101414594B (zh) 2011-01-12
WO2006030634A1 (ja) 2006-03-23
TW201041101A (en) 2010-11-16
CN100446235C (zh) 2008-12-24
KR100993151B1 (ko) 2010-11-09
CN101414593B (zh) 2011-12-21
CN101414594A (zh) 2009-04-22
US7723620B2 (en) 2010-05-25
JP4836425B2 (ja) 2011-12-14
TW201007906A (en) 2010-02-16
JP2006086283A (ja) 2006-03-30
KR20070068345A (ko) 2007-06-29
TWI331384B (zh) 2010-10-01
US20080055874A1 (en) 2008-03-06

Similar Documents

Publication Publication Date Title
CN100446235C (zh) 半导体安装用引脚和印制电路板
US5476211A (en) Method of manufacturing electrical contacts, using a sacrificial member
US5861663A (en) Column grid array or ball grid array pad on via
JP5271088B2 (ja) 超ファインピッチ配線で積層された超小型電子アセンブリとその製造方法
KR101003684B1 (ko) 패키지 기판용 리드핀
US8142240B2 (en) Lead pin for package substrate
JPH09129807A (ja) 回路パッケージの製造方法
US20060255476A1 (en) Electronic assembly with controlled solder joint thickness
KR20080031270A (ko) Ｍｏｓｆｅｔ ｂｇａ용 절곡 프레임 캐리어
JP2009043793A (ja) 半導体装置、およびその半導体装置の製造方法
JP2001044319A (ja) 配線基板およびその実装構造
JP2957547B1 (ja) ボール・グリッド・アレイ型パッケージ
Lau et al. Design, materials, and assembly process of high‐density packages with a low‐temperature lead‐free solder (SnBiAg)
JP2001339151A (ja) バンプによる電子部品の実装方法
JPH08236575A (ja) 半導体装置及びその製造方法
JPH05291432A (ja) 半導体パッケージ
WO2010089963A1 (ja) 回路基板構造体
JPH033260A (ja) Ｉｃパッケージのリード端子
US20060022327A1 (en) Enhanced PGA interconnection
JPH0282682A (ja) 多端子平面実装部品及びその実装方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CI01 Publication of corrected invention patent application

Correction item: Second inventor

Correct: Tsuruga Hiroyuki

False: Tsuruga Hiroyuki

Number: 52

Page: 1415

Volume: 24

CI03 Correction of invention patent

Correction item: Second inventor

Correct: Tsuruga Hiroyuki

False: Tsuruga Hiroyuki

Number: 52

Page: The title page

Volume: 24

ERR Gazette correction

Free format text: CORRECT: THE SECOND INVENTOR; FROM: GUO CONGRATULATES IT WIDELY TO: DUN HEKUAN