JP2006048749A5 - - Google Patents

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Publication number
JP2006048749A5
JP2006048749A5 JP2004224130A JP2004224130A JP2006048749A5 JP 2006048749 A5 JP2006048749 A5 JP 2006048749A5 JP 2004224130 A JP2004224130 A JP 2004224130A JP 2004224130 A JP2004224130 A JP 2004224130A JP 2006048749 A5 JP2006048749 A5 JP 2006048749A5
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JP
Japan
Prior art keywords
control gate
memory cell
line
cell block
selected memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004224130A
Other languages
English (en)
Japanese (ja)
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JP2006048749A (ja
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Publication date
Application filed filed Critical
Priority to JP2004224130A priority Critical patent/JP2006048749A/ja
Priority claimed from JP2004224130A external-priority patent/JP2006048749A/ja
Priority to US11/176,324 priority patent/US7292475B2/en
Priority to KR1020050068942A priority patent/KR100727203B1/ko
Priority to CNB2005100888803A priority patent/CN100520970C/zh
Publication of JP2006048749A publication Critical patent/JP2006048749A/ja
Publication of JP2006048749A5 publication Critical patent/JP2006048749A5/ja
Pending legal-status Critical Current

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JP2004224130A 2004-07-30 2004-07-30 不揮発性記憶装置及び不揮発性記憶装置のデータ書き込み方法 Pending JP2006048749A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2004224130A JP2006048749A (ja) 2004-07-30 2004-07-30 不揮発性記憶装置及び不揮発性記憶装置のデータ書き込み方法
US11/176,324 US7292475B2 (en) 2004-07-30 2005-07-08 Nonvolatile memory device and data write method for nonvolatile memory device
KR1020050068942A KR100727203B1 (ko) 2004-07-30 2005-07-28 불휘발성 기억 장치 및 불휘발성 기억 장치의 데이터 기록방법
CNB2005100888803A CN100520970C (zh) 2004-07-30 2005-07-29 非易失性存储装置以及非易失性存储装置的数据写入方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004224130A JP2006048749A (ja) 2004-07-30 2004-07-30 不揮発性記憶装置及び不揮発性記憶装置のデータ書き込み方法

Publications (2)

Publication Number Publication Date
JP2006048749A JP2006048749A (ja) 2006-02-16
JP2006048749A5 true JP2006048749A5 (enExample) 2007-01-18

Family

ID=35731975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004224130A Pending JP2006048749A (ja) 2004-07-30 2004-07-30 不揮発性記憶装置及び不揮発性記憶装置のデータ書き込み方法

Country Status (4)

Country Link
US (1) US7292475B2 (enExample)
JP (1) JP2006048749A (enExample)
KR (1) KR100727203B1 (enExample)
CN (1) CN100520970C (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4591691B2 (ja) * 2005-06-07 2010-12-01 セイコーエプソン株式会社 半導体装置
JP4548603B2 (ja) 2005-06-08 2010-09-22 セイコーエプソン株式会社 半導体装置
US7633828B2 (en) * 2006-07-31 2009-12-15 Sandisk 3D Llc Hierarchical bit line bias bus for block selectable memory array
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US8085588B2 (en) * 2009-04-30 2011-12-27 Spansion Llc Semiconductor device and control method thereof
KR101253443B1 (ko) * 2011-06-09 2013-04-11 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
KR20130120858A (ko) 2012-04-26 2013-11-05 한국전자통신연구원 전달게이트가 삽입된 이이피롬 셀
KR101982141B1 (ko) 2013-01-04 2019-05-27 한국전자통신연구원 이이피롬 셀 및 이이피롬 장치
CN111508546B (zh) * 2019-01-31 2023-06-27 群联电子股份有限公司 解码方法、存储器控制电路单元与存储器存储装置
US10706936B1 (en) 2019-04-26 2020-07-07 Western Digital Technologies, Inc. System and method for avoiding back to back program failure

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0088815B1 (de) * 1982-03-17 1985-12-18 Deutsche ITT Industries GmbH Elektrisch löschbare Speichermatrix (EEPROM)
DE3277715D1 (en) * 1982-08-06 1987-12-23 Itt Ind Gmbh Deutsche Electrically programmable memory array
FR2622038B1 (fr) * 1987-10-19 1990-01-19 Thomson Semiconducteurs Procede de programmation des cellules memoire d'une memoire et circuit pour la mise en oeuvre de ce procede
FR2623651B1 (fr) * 1987-11-20 1992-11-27 Sgs Thomson Microelectronics Plan memoire et procede et prototype de definition d'un circuit integre electronique comportant un tel plan memoire
JP2685966B2 (ja) * 1990-06-22 1997-12-08 株式会社東芝 不揮発性半導体記憶装置
US5471422A (en) * 1994-04-11 1995-11-28 Motorola, Inc. EEPROM cell with isolation transistor and methods for making and operating the same
JPH08222649A (ja) 1995-02-17 1996-08-30 Sony Corp 半導体不揮発性記憶装置
US5914514A (en) * 1996-09-27 1999-06-22 Xilinx, Inc. Two transistor flash EPROM cell
KR100252476B1 (ko) * 1997-05-19 2000-04-15 윤종용 플레이트 셀 구조의 전기적으로 소거 및 프로그램 가능한 셀들을 구비한 불 휘발성 반도체 메모리 장치및 그것의 프로그램 방법
US6643174B2 (en) * 2001-12-20 2003-11-04 Winbond Electronics Corporation EEPROM cells and array with reduced write disturbance

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