JP2006005224A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 319
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 33
- 230000003647 oxidation Effects 0.000 claims description 24
- 238000007254 oxidation reaction Methods 0.000 claims description 24
- 238000009413 insulation Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 255
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 141
- 239000000758 substrate Substances 0.000 description 53
- 239000000463 material Substances 0.000 description 33
- 238000009792 diffusion process Methods 0.000 description 18
- 230000008901 benefit Effects 0.000 description 17
- 239000012212 insulator Substances 0.000 description 17
- 229910021332 silicide Inorganic materials 0.000 description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 17
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 14
- 239000010408 film Substances 0.000 description 14
- 230000001965 increasing effect Effects 0.000 description 13
- 230000004048 modification Effects 0.000 description 11
- 238000012986 modification Methods 0.000 description 11
- 238000002955 isolation Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000006835 compression Effects 0.000 description 4
- 238000007906 compression Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/76208—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
【解決手段】 第1の半導体層1上に、第1半導体層1よりも絶縁化し難い第2半導体層3を形成する工程と、第2半導体層3の上面から第1半導体層1にかけて、第2半導体層3、及び第1半導体層1を露出させる溝7を形成する工程と、溝7から露出する第1半導体層1、及び第2半導体層3を絶縁化し、溝を、絶縁化した第1半導体層9で閉じる工程とを具備する。
【選択図】 図4
Description
図1〜図4は、この発明の第1実施形態に係る半導体装置の製造方法の一例を示す断面図である。
第2実施形態は、トレンチの幅の規定に関する例であり、様々なトレンチの幅を有した半導体装置に関する。
第3実施形態は、歪半導体の構造を持つ半導体装置において、その特性を、更に向上させる半導体装置に関する。
図23は、この発明の第3実施形態に係る半導体装置の第1変形例を示す断面図である。
図24は、この発明の第3実施形態に係る半導体装置の第2変形例を示す断面図である。
図26は、この発明の第3実施形態に係る半導体装置の第3変形例を示す断面図である。
第4実施形態は、活性領域15の幅の規定に関する。
図29は、第4実施形態に係る半導体装置の第1例を示す断面図である。
図30は、第4実施形態に係る半導体装置の第2例を示す断面図である。
図31は、第4実施形態に係る半導体装置の第3例を示す断面図である。
第4例は、第4実施形態に、第3実施形態を組み合わせた例であり、SOI構造のSi層3の周囲に、Si層3に引張力を与える引張材料71、あるいはSi層3に圧縮力を与える圧縮材料73を有する。
第5例は第4例と同様に、第4実施形態に第3実施形態を組み合わせた例である。
第6例は第4例及び第5例と同様に、第4実施形態に第3実施形態を組み合わせた例である。
図37は、この発明の第5実施形態に係る半導体装置の一例を示す断面図である。
第6実施形態は、第5実施形態に、第4実施形態の歪SOI構造を適用した例である。
第7実施形態は、歪SOI構造の他の例である。
Claims (5)
- 第1の半導体層上に、前記第1半導体層よりも絶縁化し難い第2半導体層を形成する工程と、
前記第2半導体層の上面から前記第1半導体層にかけて、前記第2半導体層、及び前記第1半導体層を露出させる溝を形成する工程と、
前記溝から露出する前記第1半導体層、及び第2半導体層を絶縁化し、前記溝を、絶縁化した第1半導体層で閉じる工程と
を具備することを特徴とする半導体装置の製造方法。 - 第1の半導体層上に、前記第1半導体層よりも絶縁化し難い第2半導体層を形成する工程と、
前記第2半導体層の上面から前記第1半導体層にかけて、前記第2半導体層、及び前記第1半導体層を露出させる溝を形成し、前記溝に挟まれたフィン状半導体構造を形成する工程と、
前記溝から露出する前記第1半導体層、及び第2半導体層を絶縁化し、前記溝を絶縁化した第1半導体層で閉じ、前記フィン状半導体構造内における前記第1半導体層の幅を前記絶縁化した第1の半導体層で狭め、前記第2半導体層を前記絶縁化した第1半導体層上にオーバーハングさせる工程と
を具備することを特徴とする半導体装置の製造方法。 - 第1の半導体層上に、前記第1半導体層よりも絶縁化し難い第2半導体層を形成する工程と、
前記第2半導体層の上面から前記第1半導体層にかけて、前記第2半導体層、及び前記第1半導体層を露出させる溝を形成し、前記溝に挟まれたフィン状半導体構造を形成する工程と、
前記溝から露出する前記第1半導体層、及び第2半導体層を絶縁化し、前記溝を絶縁化した第1半導体層で閉じ、前記フィン状半導体構造内における前記第1半導体層を前記絶縁化した第1半導体層で閉じ、前記第2半導体層を、前記絶縁化した第1半導体層上に孤立させる工程と
を具備することを特徴とする半導体装置の製造方法。 - 第1の半導体層上に、前記第1半導体層よりも絶縁化し難い第2半導体層を形成する工程と、
前記第2半導体層の上面から前記第1半導体層にかけて、前記第2半導体層、及び前記第1半導体層を露出させる溝を形成し、前記第2半導体層、及び前記第1半導体層を含み、前記溝に挟まれた第1フィン状半導体構造、及び前記第1フィン状半導体構造よりも幅が広い第2フィン状半導体構造を形成する工程と、
前記溝から露出する前記第1半導体層、及び第2半導体層を絶縁化し、前記溝を絶縁化した第1半導体層で閉じ、前記第1フィン状半導体構造内における前記第1半導体層を前記絶縁化した第1半導体層で閉じ、前記第2半導体層を、前記絶縁化した第1半導体層上に孤立させ、前記第2フィン状半導体構造内における前記第1半導体層の幅を前記絶縁化した第1の半導体層で狭め、前記第2半導体層を前記絶縁化した第1半導体層上にオーバーハングさせる工程と
を具備することを特徴とする半導体装置の製造方法。 - 前記絶縁化は、酸化であることを特徴とする請求項1乃至請求項4いずれか一項に記載の半導体装置の製造方法。
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JP2004181076A JP4473651B2 (ja) | 2004-06-18 | 2004-06-18 | 半導体装置の製造方法 |
US11/088,885 US7687368B2 (en) | 2004-06-18 | 2005-03-25 | Semiconductor device manufacturing method |
TW094119779A TWI282600B (en) | 2004-06-18 | 2005-06-15 | Fabricating method of semiconductor device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009259865A (ja) * | 2008-04-11 | 2009-11-05 | Toshiba Corp | 半導体装置、およびその製造方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101917392B1 (ko) | 2012-04-19 | 2018-11-09 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 제조방법 |
US9202917B2 (en) * | 2013-07-29 | 2015-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Buried SiGe oxide FinFET scheme for device enhancement |
US8987094B2 (en) * | 2013-07-09 | 2015-03-24 | GlobalFoundries, Inc. | FinFET integrated circuits and methods for their fabrication |
US9773705B2 (en) | 2015-06-30 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET channel on oxide structures and related methods |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4361600A (en) * | 1981-11-12 | 1982-11-30 | General Electric Company | Method of making integrated circuits |
US4604162A (en) * | 1983-06-13 | 1986-08-05 | Ncr Corporation | Formation and planarization of silicon-on-insulator structures |
JPS63308933A (ja) | 1987-06-10 | 1988-12-16 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US4849370A (en) | 1987-12-21 | 1989-07-18 | Texas Instruments Incorporated | Anodizable strain layer for SOI semiconductor structures |
JPH0389532A (ja) | 1989-08-31 | 1991-04-15 | Ricoh Co Ltd | 半導体装置の製造方法 |
US5635411A (en) * | 1991-11-12 | 1997-06-03 | Rohm Co., Ltd. | Method of making semiconductor apparatus |
US5266813A (en) * | 1992-01-24 | 1993-11-30 | International Business Machines Corporation | Isolation technique for silicon germanium devices |
JPH05291395A (ja) | 1992-04-10 | 1993-11-05 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
DE19538005A1 (de) * | 1995-10-12 | 1997-04-17 | Fraunhofer Ges Forschung | Verfahren zum Erzeugen einer Grabenisolation in einem Substrat |
US5691230A (en) * | 1996-09-04 | 1997-11-25 | Micron Technology, Inc. | Technique for producing small islands of silicon on insulator |
KR100311880B1 (ko) * | 1996-11-11 | 2001-12-20 | 미다라이 후지오 | 관통구멍의제작방법,관통구멍을갖는실리콘기판,이기판을이용한디바이스,잉크제트헤드의제조방법및잉크제트헤드 |
US5963817A (en) * | 1997-10-16 | 1999-10-05 | International Business Machines Corporation | Bulk and strained silicon on insulator using local selective oxidation |
JP2000058802A (ja) * | 1998-01-13 | 2000-02-25 | Stmicroelectronics Srl | Soiウェハの製造方法 |
EP0957515A1 (en) * | 1998-05-15 | 1999-11-17 | STMicroelectronics S.r.l. | Method for manufacturing an SOI wafer |
US6350657B1 (en) * | 1998-08-03 | 2002-02-26 | Stmicroelectronics S.R.L. | Inexpensive method of manufacturing an SOI wafer |
US6265282B1 (en) * | 1998-08-17 | 2001-07-24 | Micron Technology, Inc. | Process for making an isolation structure |
US6607948B1 (en) * | 1998-12-24 | 2003-08-19 | Kabushiki Kaisha Toshiba | Method of manufacturing a substrate using an SiGe layer |
KR100304713B1 (ko) * | 1999-10-12 | 2001-11-02 | 윤종용 | 부분적인 soi 구조를 갖는 반도체소자 및 그 제조방법 |
JP2002203894A (ja) * | 2001-01-04 | 2002-07-19 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
EP1397832A2 (en) * | 2001-06-08 | 2004-03-17 | Amberwave Systems Corporation | Method for isolating semiconductor devices |
US6900094B2 (en) * | 2001-06-14 | 2005-05-31 | Amberwave Systems Corporation | Method of selective removal of SiGe alloys |
US6891209B2 (en) * | 2001-08-13 | 2005-05-10 | Amberwave Systems Corporation | Dynamic random access memory trench capacitors |
US6600170B1 (en) * | 2001-12-17 | 2003-07-29 | Advanced Micro Devices, Inc. | CMOS with strained silicon channel NMOS and silicon germanium channel PMOS |
JP4136939B2 (ja) * | 2002-01-09 | 2008-08-20 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
US6627515B1 (en) * | 2002-12-13 | 2003-09-30 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a non-floating body device with enhanced performance |
US6800917B2 (en) * | 2002-12-17 | 2004-10-05 | Texas Instruments Incorporated | Bladed silicon-on-insulator semiconductor devices and method of making |
US6846720B2 (en) * | 2003-06-18 | 2005-01-25 | Agency For Science, Technology And Research | Method to reduce junction leakage current in strained silicon on silicon-germanium devices |
US7153753B2 (en) * | 2003-08-05 | 2006-12-26 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
US7211474B2 (en) * | 2005-01-18 | 2007-05-01 | International Business Machines Corporation | SOI device with body contact self-aligned to gate |
-
2004
- 2004-06-18 JP JP2004181076A patent/JP4473651B2/ja active Active
-
2005
- 2005-03-25 US US11/088,885 patent/US7687368B2/en not_active Expired - Fee Related
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009259865A (ja) * | 2008-04-11 | 2009-11-05 | Toshiba Corp | 半導体装置、およびその製造方法 |
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US20050282354A1 (en) | 2005-12-22 |
TWI282600B (en) | 2007-06-11 |
JP4473651B2 (ja) | 2010-06-02 |
US7687368B2 (en) | 2010-03-30 |
TW200601490A (en) | 2006-01-01 |
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