JP2006005207A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2006005207A
JP2006005207A JP2004180722A JP2004180722A JP2006005207A JP 2006005207 A JP2006005207 A JP 2006005207A JP 2004180722 A JP2004180722 A JP 2004180722A JP 2004180722 A JP2004180722 A JP 2004180722A JP 2006005207 A JP2006005207 A JP 2006005207A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor layer
layer
electrode
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004180722A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006005207A5 (https=
Inventor
Hisashi Toyoda
久志 豊田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2004180722A priority Critical patent/JP2006005207A/ja
Publication of JP2006005207A publication Critical patent/JP2006005207A/ja
Publication of JP2006005207A5 publication Critical patent/JP2006005207A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H10W72/9232—Bond pads having multiple stacked layers with additional elements interposed between layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2004180722A 2004-06-18 2004-06-18 半導体装置 Pending JP2006005207A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004180722A JP2006005207A (ja) 2004-06-18 2004-06-18 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004180722A JP2006005207A (ja) 2004-06-18 2004-06-18 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007142792A Division JP2007266621A (ja) 2007-05-30 2007-05-30 半導体装置

Publications (2)

Publication Number Publication Date
JP2006005207A true JP2006005207A (ja) 2006-01-05
JP2006005207A5 JP2006005207A5 (https=) 2007-07-12

Family

ID=35773313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004180722A Pending JP2006005207A (ja) 2004-06-18 2004-06-18 半導体装置

Country Status (1)

Country Link
JP (1) JP2006005207A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007243140A (ja) * 2006-02-09 2007-09-20 Renesas Technology Corp 半導体装置、電子装置および半導体装置の製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130757A (ja) * 1993-10-28 1995-05-19 Sony Corp バイポーラトランジスタの製造方法
JP2004128142A (ja) * 2002-10-01 2004-04-22 Nec Compound Semiconductor Devices Ltd 半導体装置及びその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130757A (ja) * 1993-10-28 1995-05-19 Sony Corp バイポーラトランジスタの製造方法
JP2004128142A (ja) * 2002-10-01 2004-04-22 Nec Compound Semiconductor Devices Ltd 半導体装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007243140A (ja) * 2006-02-09 2007-09-20 Renesas Technology Corp 半導体装置、電子装置および半導体装置の製造方法

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