JP2005514765A - エッチング停止層としてポリシリコン再酸化層を使用することによって、シリコン層の凹部を減少する窒化オフセットスペーサ - Google Patents

エッチング停止層としてポリシリコン再酸化層を使用することによって、シリコン層の凹部を減少する窒化オフセットスペーサ Download PDF

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JP2005514765A
JP2005514765A JP2003555572A JP2003555572A JP2005514765A JP 2005514765 A JP2005514765 A JP 2005514765A JP 2003555572 A JP2003555572 A JP 2003555572A JP 2003555572 A JP2003555572 A JP 2003555572A JP 2005514765 A JP2005514765 A JP 2005514765A
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layer
substrate
forming
polysilicon
nitride
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JP2003555572A
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JP2005514765A5 (https=
Inventor
キ ウェン−ジー
ジー． ペレリン ジョン
ジー． エン ウィリアム
ダブリュ． マイケル マーク
エイ． チャン ダリン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01354—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
JP2003555572A 2001-12-20 2002-12-19 エッチング停止層としてポリシリコン再酸化層を使用することによって、シリコン層の凹部を減少する窒化オフセットスペーサ Pending JP2005514765A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/023,328 US6780776B1 (en) 2001-12-20 2001-12-20 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer
PCT/US2002/041105 WO2003054948A1 (en) 2001-12-20 2002-12-19 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer

Publications (2)

Publication Number Publication Date
JP2005514765A true JP2005514765A (ja) 2005-05-19
JP2005514765A5 JP2005514765A5 (https=) 2006-02-09

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Family Applications (1)

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JP2003555572A Pending JP2005514765A (ja) 2001-12-20 2002-12-19 エッチング停止層としてポリシリコン再酸化層を使用することによって、シリコン層の凹部を減少する窒化オフセットスペーサ

Country Status (7)

Country Link
US (1) US6780776B1 (https=)
EP (1) EP1456874A1 (https=)
JP (1) JP2005514765A (https=)
KR (1) KR100945915B1 (https=)
CN (1) CN100367470C (https=)
AU (1) AU2002358271A1 (https=)
WO (1) WO2003054948A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8552507B2 (en) 2009-12-24 2013-10-08 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100721200B1 (ko) * 2005-12-22 2007-05-23 주식회사 하이닉스반도체 반도체소자의 듀얼 게이트 형성방법
US8410539B2 (en) * 2006-02-14 2013-04-02 Stmicroelectronics (Crolles 2) Sas MOS transistor with a settable threshold
US7544561B2 (en) * 2006-11-06 2009-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation
KR100874957B1 (ko) * 2007-02-26 2008-12-19 삼성전자주식회사 오프셋 스페이서를 갖는 반도체 소자의 제조방법 및 관련된소자
JP2008098640A (ja) * 2007-10-09 2008-04-24 Toshiba Corp 半導体装置の製造方法
US8854403B2 (en) * 2009-02-06 2014-10-07 Xerox Corporation Image forming apparatus with a TFT backplane for xerography without a light source
CN108206160B (zh) * 2016-12-20 2020-11-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置

Citations (3)

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JPH053206A (ja) * 1990-08-29 1993-01-08 Toshiba Corp オフセツトゲート構造トランジスタおよびその製造方法
JPH05102185A (ja) * 1991-04-01 1993-04-23 Sgs Thomson Microelectron Inc 改良型電界効果トランジスタ構成体及び製造方法
JPH07142726A (ja) * 1993-11-19 1995-06-02 Oki Electric Ind Co Ltd 電界効果型トランジスタの製造方法

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GB2219434A (en) 1988-06-06 1989-12-06 Philips Nv A method of forming a contact in a semiconductor device
US5783475A (en) * 1995-11-13 1998-07-21 Motorola, Inc. Method of forming a spacer
US5670404A (en) 1996-06-21 1997-09-23 Industrial Technology Research Institute Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer
US5899719A (en) * 1997-02-14 1999-05-04 United Semiconductor Corporation Sub-micron MOSFET
US6063698A (en) * 1997-06-30 2000-05-16 Motorola, Inc. Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits
US5912188A (en) 1997-08-04 1999-06-15 Advanced Micro Devices, Inc. Method of forming a contact hole in an interlevel dielectric layer using dual etch stops
US6165831A (en) 1998-11-20 2000-12-26 United Microelectronics Corp. Method of fabricating a buried contact in a static random access memory
US6187645B1 (en) 1999-01-19 2001-02-13 United Microelectronics Corp. Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation
US6294432B1 (en) 1999-12-20 2001-09-25 United Microelectronics Corp. Super halo implant combined with offset spacer process
TW463251B (en) * 2000-12-08 2001-11-11 Macronix Int Co Ltd Manufacturing method of gate structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH053206A (ja) * 1990-08-29 1993-01-08 Toshiba Corp オフセツトゲート構造トランジスタおよびその製造方法
JPH05102185A (ja) * 1991-04-01 1993-04-23 Sgs Thomson Microelectron Inc 改良型電界効果トランジスタ構成体及び製造方法
JPH07142726A (ja) * 1993-11-19 1995-06-02 Oki Electric Ind Co Ltd 電界効果型トランジスタの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8552507B2 (en) 2009-12-24 2013-10-08 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
EP1456874A1 (en) 2004-09-15
CN1606798A (zh) 2005-04-13
KR100945915B1 (ko) 2010-03-05
CN100367470C (zh) 2008-02-06
KR20040068964A (ko) 2004-08-02
AU2002358271A1 (en) 2003-07-09
WO2003054948A1 (en) 2003-07-03
US6780776B1 (en) 2004-08-24

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