JP2005510872A - シリコン欠乏雰囲気中のｐｅｃｖｄプロセスを用いた、金属ゲート電極のための酸窒化物スペーサの形成方法 - Google Patents

シリコン欠乏雰囲気中のｐｅｃｖｄプロセスを用いた、金属ゲート電極のための酸窒化物スペーサの形成方法 Download PDF

Info

Publication number
JP2005510872A
JP2005510872A JP2003548295A JP2003548295A JP2005510872A JP 2005510872 A JP2005510872 A JP 2005510872A JP 2003548295 A JP2003548295 A JP 2003548295A JP 2003548295 A JP2003548295 A JP 2003548295A JP 2005510872 A JP2005510872 A JP 2005510872A
Authority
JP
Japan
Prior art keywords
silicon
gate electrode
metal gate
silicon oxynitride
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003548295A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005510872A5 (https=
Inventor
バン エヌジーオー ミン
ハリヤル アービンド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2005510872A publication Critical patent/JP2005510872A/ja
Publication of JP2005510872A5 publication Critical patent/JP2005510872A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/308—Oxynitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6927—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01316—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane

Landscapes

  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)
JP2003548295A 2001-11-26 2002-10-11 シリコン欠乏雰囲気中のｐｅｃｖｄプロセスを用いた、金属ゲート電極のための酸窒化物スペーサの形成方法 Pending JP2005510872A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/994,128 US6509282B1 (en) 2001-11-26 2001-11-26 Silicon-starved PECVD method for metal gate electrode dielectric spacer
PCT/US2002/032582 WO2003046971A1 (en) 2001-11-26 2002-10-11 Method for forming an oxynitride spacer for a metal gate electrode using a pecvd process with a silicon-starving atmosphere

Publications (2)

Publication Number Publication Date
JP2005510872A true JP2005510872A (ja) 2005-04-21
JP2005510872A5 JP2005510872A5 (https=) 2006-08-03

Family

ID=25540311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003548295A Pending JP2005510872A (ja) 2001-11-26 2002-10-11 シリコン欠乏雰囲気中のｐｅｃｖｄプロセスを用いた、金属ゲート電極のための酸窒化物スペーサの形成方法

Country Status (7)

Country Link
US (2) US6509282B1 (https=)
EP (1) EP1449243A1 (https=)
JP (1) JP2005510872A (https=)
KR (1) KR100891367B1 (https=)
CN (1) CN100355043C (https=)
AU (1) AU2002347877A1 (https=)
WO (1) WO2003046971A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006024609A (ja) * 2004-07-06 2006-01-26 Sony Corp 半導体装置およびその製造方法

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4659329B2 (ja) * 2000-06-26 2011-03-30 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US20040212025A1 (en) * 2003-04-28 2004-10-28 Wilman Tsai High k oxide
JP4511307B2 (ja) * 2004-02-10 2010-07-28 セイコーエプソン株式会社 ゲート絶縁膜、半導体素子、電子デバイスおよび電子機器
US7102191B2 (en) * 2004-03-24 2006-09-05 Micron Technologies, Inc. Memory device with high dielectric constant gate dielectrics and metal floating gates
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
KR100688575B1 (ko) * 2004-10-08 2007-03-02 삼성전자주식회사 비휘발성 반도체 메모리 소자
US20060094194A1 (en) * 2004-11-04 2006-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology
US7732923B2 (en) * 2004-12-30 2010-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Impurity doped UV protection layer
KR100771808B1 (ko) * 2006-07-05 2007-10-30 주식회사 하이닉스반도체 Ｓｏｎｏｓ 구조를 갖는 플래시 메모리 소자 및 그것의제조 방법
KR100819706B1 (ko) * 2006-12-27 2008-04-04 동부일렉트로닉스 주식회사 씨모스 이미지센서 및 그 제조방법
DE202007001431U1 (de) * 2007-01-31 2007-05-16 Infineon Technologies Austria Ag Halbleiteranordnung und Leistungshalbleiterbauelement
JP5358893B2 (ja) * 2007-04-03 2013-12-04 三菱電機株式会社 トランジスタ
US20080246099A1 (en) * 2007-04-09 2008-10-09 Ajith Varghese Low temperature poly oxide processes for high-k/metal gate flow
CN102157360B (zh) * 2010-02-11 2012-12-12 中芯国际集成电路制造(上海)有限公司 一种栅极制造方法
US8936965B2 (en) * 2010-11-26 2015-01-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8822283B2 (en) * 2011-09-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned insulated film for high-k metal gate device
KR102309244B1 (ko) 2013-02-20 2021-10-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US9799829B2 (en) 2014-07-25 2017-10-24 Semiconductor Energy Laboratory Co., Ltd. Separation method, light-emitting device, module, and electronic device
US11223289B2 (en) 2020-01-17 2022-01-11 Astec International Limited Regulated switched mode power supplies having adjustable output voltages
CN111540673B (zh) * 2020-07-07 2020-10-16 中芯集成电路制造(绍兴)有限公司 半导体器件的形成方法
KR102608390B1 (ko) 2021-07-06 2023-12-01 한국과학기술연구원 내구성이 우수한 컬러링 금속 부재 및 이의 제조방법

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63184340A (ja) * 1986-09-08 1988-07-29 Nec Corp 半導体装置
JPH01173635A (ja) * 1987-12-28 1989-07-10 Nissan Motor Co Ltd 半導体装置の製造方法
JPH04209543A (ja) * 1990-12-06 1992-07-30 Seiko Instr Inc 半導体装置の製造方法
JPH0684888A (ja) * 1992-02-27 1994-03-25 G T C:Kk 絶縁膜の形成方法
JPH06310504A (ja) * 1993-04-27 1994-11-04 Nec Corp 絶縁膜の構造とその製造方法
JPH08102449A (ja) * 1994-08-23 1996-04-16 Texas Instr Inc <Ti> 有機含有誘電率材料を用いた自己整合コンタクト
JP2000091337A (ja) * 1998-09-09 2000-03-31 Toshiba Microelectronics Corp 半導体装置及びその製造方法
JP2001176878A (ja) * 1999-12-21 2001-06-29 Furontekku:Kk 銅配線基板およびその製造方法ならびに液晶表示装置
JP2001308086A (ja) * 2000-04-18 2001-11-02 Nec Corp 膜形成方法

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US444124A (en) * 1891-01-06 Matrix making machine
US4441247A (en) 1981-06-29 1984-04-10 Intel Corporation Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate
US4648175A (en) 1985-06-12 1987-03-10 Ncr Corporation Use of selectively deposited tungsten for contact formation and shunting metallization
JPS63316476A (ja) 1987-06-18 1988-12-23 Seiko Instr & Electronics Ltd 半導体装置およびその製造方法
US4854263B1 (en) 1987-08-14 1997-06-17 Applied Materials Inc Inlet manifold and methods for increasing gas dissociation and for PECVD of dielectric films
GB2244860A (en) 1990-06-04 1991-12-11 Philips Electronic Associated Fabricating mim type device array and display devices incorporating such arrays
FR2670605B1 (fr) 1990-12-13 1993-04-09 France Etat Procede de realisation d'une barriere de diffusion electriquement conductrice a l'interface metal/silicium d'un transistor mos et transistor correspondant.
GB9206086D0 (en) 1992-03-20 1992-05-06 Philips Electronics Uk Ltd Manufacturing electronic devices comprising,e.g.tfts and mims
EP0661732B1 (en) * 1993-12-28 2004-06-09 Applied Materials, Inc. A method of forming silicon oxy-nitride films by plasma-enhanced chemical vapor deposition
NZ280375A (en) 1996-05-01 1998-09-24 Ind Res Ltd A silicon oxynitride ceramic material characterised by its x-ray powder diffraction trace
TW320752B (en) 1996-11-18 1997-11-21 United Microelectronics Corp Metal gate electrode process
US5930627A (en) 1997-05-05 1999-07-27 Chartered Semiconductor Manufacturing Company, Ltd. Process improvements in self-aligned polysilicon MOSFET technology using silicon oxynitride
US5989957A (en) 1997-05-21 1999-11-23 Advanced Micro Devices Process for fabricating semiconductor memory device with high data retention including silicon oxynitride etch stop layer formed at high temperature with low hydrogen ion concentration
JPH11233451A (ja) 1997-10-07 1999-08-27 Texas Instr Inc <Ti> 安定した低抵抗のポリ・メタル・ゲート電極を製造するためのｃｖｄに基くプロセス
US6051487A (en) 1997-12-18 2000-04-18 Advanced Micro Devices, Inc. Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode
US6140190A (en) * 1997-12-18 2000-10-31 Advanced Micro Devices Method and structure for elevated source/drain with polished gate electrode insulated gate field effect transistors
US6274421B1 (en) 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
US6225168B1 (en) 1998-06-04 2001-05-01 Advanced Micro Devices, Inc. Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof
US6200734B1 (en) * 1998-06-15 2001-03-13 Lucent Technologies Inc. Method for fabricating semiconductor devices
US6107171A (en) 1998-07-09 2000-08-22 Vanguard International Semiconductor Corporation Method to manufacture metal gate of integrated circuits
US6110779A (en) 1998-07-17 2000-08-29 Advanced Micro Devices, Inc. Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride
US6100559A (en) * 1998-08-14 2000-08-08 Advanced Micro Devices, Inc. Multipurpose graded silicon oxynitride cap layer
US6066533A (en) 1998-09-29 2000-05-23 Advanced Micro Devices, Inc. MOS transistor with dual metal gate structure
US6245605B1 (en) 1998-09-29 2001-06-12 Texas Instruments Incorporated Method to protect metal from oxidation during poly-metal gate formation in semiconductor device manufacturing
US6162694A (en) 1998-11-25 2000-12-19 Advanced Micro Devices, Inc. Method of forming a metal gate electrode using replaced polysilicon structure
US6221794B1 (en) * 1998-12-08 2001-04-24 Advanced Micro Devices, Inc. Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines
KR100300628B1 (ko) * 1999-02-08 2001-09-26 윤종용 실리콘 옥시나이트라이드 보호층을 갖는 반도체 장치 및 그 제조 방법
US6291282B1 (en) * 1999-02-26 2001-09-18 Texas Instruments Incorporated Method of forming dual metal gate structures or CMOS devices
US6096656A (en) 1999-06-24 2000-08-01 Sandia Corporation Formation of microchannels from low-temperature plasma-deposited silicon oxynitride
US6046103A (en) * 1999-08-02 2000-04-04 Taiwan Semiconductor Manufacturing Company Borderless contact process for a salicide devices
US6372668B2 (en) * 2000-01-18 2002-04-16 Advanced Micro Devices, Inc. Method of forming silicon oxynitride films
US6670695B1 (en) * 2000-02-29 2003-12-30 United Microelectronics Corp. Method of manufacturing anti-reflection layer

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63184340A (ja) * 1986-09-08 1988-07-29 Nec Corp 半導体装置
JPH01173635A (ja) * 1987-12-28 1989-07-10 Nissan Motor Co Ltd 半導体装置の製造方法
JPH04209543A (ja) * 1990-12-06 1992-07-30 Seiko Instr Inc 半導体装置の製造方法
JPH0684888A (ja) * 1992-02-27 1994-03-25 G T C:Kk 絶縁膜の形成方法
JPH06310504A (ja) * 1993-04-27 1994-11-04 Nec Corp 絶縁膜の構造とその製造方法
JPH08102449A (ja) * 1994-08-23 1996-04-16 Texas Instr Inc <Ti> 有機含有誘電率材料を用いた自己整合コンタクト
JP2000091337A (ja) * 1998-09-09 2000-03-31 Toshiba Microelectronics Corp 半導体装置及びその製造方法
JP2001176878A (ja) * 1999-12-21 2001-06-29 Furontekku:Kk 銅配線基板およびその製造方法ならびに液晶表示装置
JP2001308086A (ja) * 2000-04-18 2001-11-02 Nec Corp 膜形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006024609A (ja) * 2004-07-06 2006-01-26 Sony Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
CN100355043C (zh) 2007-12-12
CN1592959A (zh) 2005-03-09
US20030098487A1 (en) 2003-05-29
EP1449243A1 (en) 2004-08-25
KR20040060991A (ko) 2004-07-06
US6605848B2 (en) 2003-08-12
KR100891367B1 (ko) 2009-04-02
US6509282B1 (en) 2003-01-21
AU2002347877A1 (en) 2003-06-10
WO2003046971A1 (en) 2003-06-05

Similar Documents

Publication Publication Date Title
KR100891367B1 (ko) 실리콘 결핍 분위기에서 ｐｅｃｖｄ 공정을 사용하여 금속 게이트 전극용 옥시나이트라이드 스페이서를 제조하는 방법
US8168502B2 (en) Tantalum silicon oxynitride high-K dielectrics and metal gates
US8557672B2 (en) Dielectrics containing at least one of a refractory metal or a non-refractory metal
CN102714177B (zh) 具有带氧阻障层的金属栅极堆叠的场效应晶体管器件
US7605030B2 (en) Hafnium tantalum oxynitride high-k dielectric and metal gates
US9653300B2 (en) Structure of metal gate structure and manufacturing method of the same
JP2008078675A (ja) 高誘電率絶縁膜を有する半導体装置
KR20070093898A (ko) 비휘발성 반도체 메모리 장치
TWI919254B (zh) 半導體裝置和製造半導體裝置的方法
KR102957413B1 (ko) 반도체 디바이스에서의 확산 배리어층
US20250366148A1 (en) Diffusion barrier layers in semiconductor devices
JP2005191341A (ja) 半導体装置とその製造方法
JP2006012900A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051007

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060615

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070620

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090616

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20090916

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20090928

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091009

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100112

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100430

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20100519

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20100702

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20100714

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20100902