CN100355043C - 具有金属栅极电极的半导体装置及其制程 - Google Patents
具有金属栅极电极的半导体装置及其制程 Download PDFInfo
- Publication number
- CN100355043C CN100355043C CNB02823443XA CN02823443A CN100355043C CN 100355043 C CN100355043 C CN 100355043C CN B02823443X A CNB02823443X A CN B02823443XA CN 02823443 A CN02823443 A CN 02823443A CN 100355043 C CN100355043 C CN 100355043C
- Authority
- CN
- China
- Prior art keywords
- silicon
- gate electrode
- metal gate
- silicon oxynitride
- supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/308—Oxynitrides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H10P14/6927—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01316—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
- H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
- H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
Landscapes
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/994,128 | 2001-11-26 | ||
| US09/994,128 US6509282B1 (en) | 2001-11-26 | 2001-11-26 | Silicon-starved PECVD method for metal gate electrode dielectric spacer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1592959A CN1592959A (zh) | 2005-03-09 |
| CN100355043C true CN100355043C (zh) | 2007-12-12 |
Family
ID=25540311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB02823443XA Expired - Fee Related CN100355043C (zh) | 2001-11-26 | 2002-10-11 | 具有金属栅极电极的半导体装置及其制程 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US6509282B1 (https=) |
| EP (1) | EP1449243A1 (https=) |
| JP (1) | JP2005510872A (https=) |
| KR (1) | KR100891367B1 (https=) |
| CN (1) | CN100355043C (https=) |
| AU (1) | AU2002347877A1 (https=) |
| WO (1) | WO2003046971A1 (https=) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4659329B2 (ja) * | 2000-06-26 | 2011-03-30 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
| US20040212025A1 (en) * | 2003-04-28 | 2004-10-28 | Wilman Tsai | High k oxide |
| JP4511307B2 (ja) * | 2004-02-10 | 2010-07-28 | セイコーエプソン株式会社 | ゲート絶縁膜、半導体素子、電子デバイスおよび電子機器 |
| US7102191B2 (en) * | 2004-03-24 | 2006-09-05 | Micron Technologies, Inc. | Memory device with high dielectric constant gate dielectrics and metal floating gates |
| JP4876375B2 (ja) * | 2004-07-06 | 2012-02-15 | ソニー株式会社 | 半導体装置およびその製造方法 |
| US7332439B2 (en) * | 2004-09-29 | 2008-02-19 | Intel Corporation | Metal gate transistors with epitaxial source and drain regions |
| KR100688575B1 (ko) * | 2004-10-08 | 2007-03-02 | 삼성전자주식회사 | 비휘발성 반도체 메모리 소자 |
| US20060094194A1 (en) * | 2004-11-04 | 2006-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology |
| US7732923B2 (en) * | 2004-12-30 | 2010-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Impurity doped UV protection layer |
| KR100771808B1 (ko) * | 2006-07-05 | 2007-10-30 | 주식회사 하이닉스반도체 | Sonos 구조를 갖는 플래시 메모리 소자 및 그것의제조 방법 |
| KR100819706B1 (ko) * | 2006-12-27 | 2008-04-04 | 동부일렉트로닉스 주식회사 | 씨모스 이미지센서 및 그 제조방법 |
| DE202007001431U1 (de) * | 2007-01-31 | 2007-05-16 | Infineon Technologies Austria Ag | Halbleiteranordnung und Leistungshalbleiterbauelement |
| JP5358893B2 (ja) * | 2007-04-03 | 2013-12-04 | 三菱電機株式会社 | トランジスタ |
| US20080246099A1 (en) * | 2007-04-09 | 2008-10-09 | Ajith Varghese | Low temperature poly oxide processes for high-k/metal gate flow |
| CN102157360B (zh) * | 2010-02-11 | 2012-12-12 | 中芯国际集成电路制造(上海)有限公司 | 一种栅极制造方法 |
| US8936965B2 (en) * | 2010-11-26 | 2015-01-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US8822283B2 (en) * | 2011-09-02 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned insulated film for high-k metal gate device |
| KR102309244B1 (ko) | 2013-02-20 | 2021-10-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
| US9799829B2 (en) | 2014-07-25 | 2017-10-24 | Semiconductor Energy Laboratory Co., Ltd. | Separation method, light-emitting device, module, and electronic device |
| US11223289B2 (en) | 2020-01-17 | 2022-01-11 | Astec International Limited | Regulated switched mode power supplies having adjustable output voltages |
| CN111540673B (zh) * | 2020-07-07 | 2020-10-16 | 中芯集成电路制造(绍兴)有限公司 | 半导体器件的形成方法 |
| KR102608390B1 (ko) | 2021-07-06 | 2023-12-01 | 한국과학기술연구원 | 내구성이 우수한 컬러링 금속 부재 및 이의 제조방법 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4441247A (en) * | 1981-06-29 | 1984-04-10 | Intel Corporation | Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate |
| US4648175A (en) * | 1985-06-12 | 1987-03-10 | Ncr Corporation | Use of selectively deposited tungsten for contact formation and shunting metallization |
| US5300455A (en) * | 1990-12-13 | 1994-04-05 | France Telecom | Process for producing an electrically conductive diffusion barrier at the metal/silicon interface of a MOS transistor |
| CN1266277A (zh) * | 1999-02-26 | 2000-09-13 | 德克萨斯仪器股份有限公司 | 形成cmos器件的双金属栅结构的方法 |
Family Cites Families (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US444124A (en) * | 1891-01-06 | Matrix making machine | ||
| JPS63184340A (ja) * | 1986-09-08 | 1988-07-29 | Nec Corp | 半導体装置 |
| JPS63316476A (ja) | 1987-06-18 | 1988-12-23 | Seiko Instr & Electronics Ltd | 半導体装置およびその製造方法 |
| US4854263B1 (en) | 1987-08-14 | 1997-06-17 | Applied Materials Inc | Inlet manifold and methods for increasing gas dissociation and for PECVD of dielectric films |
| JPH01173635A (ja) * | 1987-12-28 | 1989-07-10 | Nissan Motor Co Ltd | 半導体装置の製造方法 |
| GB2244860A (en) | 1990-06-04 | 1991-12-11 | Philips Electronic Associated | Fabricating mim type device array and display devices incorporating such arrays |
| JPH04209543A (ja) * | 1990-12-06 | 1992-07-30 | Seiko Instr Inc | 半導体装置の製造方法 |
| JP2506539B2 (ja) * | 1992-02-27 | 1996-06-12 | 株式会社ジーティシー | 絶縁膜の形成方法 |
| GB9206086D0 (en) | 1992-03-20 | 1992-05-06 | Philips Electronics Uk Ltd | Manufacturing electronic devices comprising,e.g.tfts and mims |
| JP2722989B2 (ja) * | 1993-04-27 | 1998-03-09 | 日本電気株式会社 | 配線の埋め込み方法 |
| EP0661732B1 (en) * | 1993-12-28 | 2004-06-09 | Applied Materials, Inc. | A method of forming silicon oxy-nitride films by plasma-enhanced chemical vapor deposition |
| US5482894A (en) * | 1994-08-23 | 1996-01-09 | Texas Instruments Incorporated | Method of fabricating a self-aligned contact using organic dielectric materials |
| NZ280375A (en) | 1996-05-01 | 1998-09-24 | Ind Res Ltd | A silicon oxynitride ceramic material characterised by its x-ray powder diffraction trace |
| TW320752B (en) | 1996-11-18 | 1997-11-21 | United Microelectronics Corp | Metal gate electrode process |
| US5930627A (en) | 1997-05-05 | 1999-07-27 | Chartered Semiconductor Manufacturing Company, Ltd. | Process improvements in self-aligned polysilicon MOSFET technology using silicon oxynitride |
| US5989957A (en) | 1997-05-21 | 1999-11-23 | Advanced Micro Devices | Process for fabricating semiconductor memory device with high data retention including silicon oxynitride etch stop layer formed at high temperature with low hydrogen ion concentration |
| JPH11233451A (ja) | 1997-10-07 | 1999-08-27 | Texas Instr Inc <Ti> | 安定した低抵抗のポリ・メタル・ゲート電極を製造するためのcvdに基くプロセス |
| US6051487A (en) | 1997-12-18 | 2000-04-18 | Advanced Micro Devices, Inc. | Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode |
| US6140190A (en) * | 1997-12-18 | 2000-10-31 | Advanced Micro Devices | Method and structure for elevated source/drain with polished gate electrode insulated gate field effect transistors |
| US6274421B1 (en) | 1998-01-09 | 2001-08-14 | Sharp Laboratories Of America, Inc. | Method of making metal gate sub-micron MOS transistor |
| US6225168B1 (en) | 1998-06-04 | 2001-05-01 | Advanced Micro Devices, Inc. | Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof |
| US6200734B1 (en) * | 1998-06-15 | 2001-03-13 | Lucent Technologies Inc. | Method for fabricating semiconductor devices |
| US6107171A (en) | 1998-07-09 | 2000-08-22 | Vanguard International Semiconductor Corporation | Method to manufacture metal gate of integrated circuits |
| US6110779A (en) | 1998-07-17 | 2000-08-29 | Advanced Micro Devices, Inc. | Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride |
| US6100559A (en) * | 1998-08-14 | 2000-08-08 | Advanced Micro Devices, Inc. | Multipurpose graded silicon oxynitride cap layer |
| JP2000091337A (ja) * | 1998-09-09 | 2000-03-31 | Toshiba Microelectronics Corp | 半導体装置及びその製造方法 |
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| US6245605B1 (en) | 1998-09-29 | 2001-06-12 | Texas Instruments Incorporated | Method to protect metal from oxidation during poly-metal gate formation in semiconductor device manufacturing |
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| KR100300628B1 (ko) * | 1999-02-08 | 2001-09-26 | 윤종용 | 실리콘 옥시나이트라이드 보호층을 갖는 반도체 장치 및 그 제조 방법 |
| US6096656A (en) | 1999-06-24 | 2000-08-01 | Sandia Corporation | Formation of microchannels from low-temperature plasma-deposited silicon oxynitride |
| US6046103A (en) * | 1999-08-02 | 2000-04-04 | Taiwan Semiconductor Manufacturing Company | Borderless contact process for a salicide devices |
| JP4243401B2 (ja) * | 1999-12-21 | 2009-03-25 | エルジー ディスプレイ カンパニー リミテッド | 銅配線基板およびその製造方法ならびに液晶表示装置 |
| US6372668B2 (en) * | 2000-01-18 | 2002-04-16 | Advanced Micro Devices, Inc. | Method of forming silicon oxynitride films |
| US6670695B1 (en) * | 2000-02-29 | 2003-12-30 | United Microelectronics Corp. | Method of manufacturing anti-reflection layer |
| JP2001308086A (ja) * | 2000-04-18 | 2001-11-02 | Nec Corp | 膜形成方法 |
-
2001
- 2001-11-26 US US09/994,128 patent/US6509282B1/en not_active Expired - Fee Related
-
2002
- 2002-09-18 US US10/246,267 patent/US6605848B2/en not_active Expired - Lifetime
- 2002-10-11 CN CNB02823443XA patent/CN100355043C/zh not_active Expired - Fee Related
- 2002-10-11 JP JP2003548295A patent/JP2005510872A/ja active Pending
- 2002-10-11 EP EP02784088A patent/EP1449243A1/en not_active Withdrawn
- 2002-10-11 KR KR1020047007987A patent/KR100891367B1/ko not_active Expired - Fee Related
- 2002-10-11 WO PCT/US2002/032582 patent/WO2003046971A1/en not_active Ceased
- 2002-10-11 AU AU2002347877A patent/AU2002347877A1/en not_active Abandoned
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4441247A (en) * | 1981-06-29 | 1984-04-10 | Intel Corporation | Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate |
| US4648175A (en) * | 1985-06-12 | 1987-03-10 | Ncr Corporation | Use of selectively deposited tungsten for contact formation and shunting metallization |
| US5300455A (en) * | 1990-12-13 | 1994-04-05 | France Telecom | Process for producing an electrically conductive diffusion barrier at the metal/silicon interface of a MOS transistor |
| CN1266277A (zh) * | 1999-02-26 | 2000-09-13 | 德克萨斯仪器股份有限公司 | 形成cmos器件的双金属栅结构的方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1592959A (zh) | 2005-03-09 |
| US20030098487A1 (en) | 2003-05-29 |
| EP1449243A1 (en) | 2004-08-25 |
| KR20040060991A (ko) | 2004-07-06 |
| US6605848B2 (en) | 2003-08-12 |
| KR100891367B1 (ko) | 2009-04-02 |
| US6509282B1 (en) | 2003-01-21 |
| AU2002347877A1 (en) | 2003-06-10 |
| JP2005510872A (ja) | 2005-04-21 |
| WO2003046971A1 (en) | 2003-06-05 |
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Owner name: ADVANCED MICRO DEVICES INC Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC. Effective date: 20100709 |
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Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA, USA TO: GRAND CAYMAN ISLAND RITISH CAYMAN ISLANDS |
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Effective date of registration: 20100709 Address after: Grand Cayman, Cayman Islands Patentee after: Globalfoundries Semiconductor Inc. Address before: American California Patentee before: Advanced Micro Devices Inc. |
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