JP2005250650A5 - - Google Patents

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Publication number
JP2005250650A5
JP2005250650A5 JP2004057598A JP2004057598A JP2005250650A5 JP 2005250650 A5 JP2005250650 A5 JP 2005250650A5 JP 2004057598 A JP2004057598 A JP 2004057598A JP 2004057598 A JP2004057598 A JP 2004057598A JP 2005250650 A5 JP2005250650 A5 JP 2005250650A5
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JP
Japan
Prior art keywords
master
clock
slave
signal
activation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004057598A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005250650A (ja
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Publication date
Application filed filed Critical
Priority to JP2004057598A priority Critical patent/JP2005250650A/ja
Priority claimed from JP2004057598A external-priority patent/JP2005250650A/ja
Priority to US11/068,753 priority patent/US7277976B2/en
Priority to CNB2005100531069A priority patent/CN1332282C/zh
Priority to KR1020050017456A priority patent/KR20060043346A/ko
Publication of JP2005250650A publication Critical patent/JP2005250650A/ja
Publication of JP2005250650A5 publication Critical patent/JP2005250650A5/ja
Priority to KR1020070032519A priority patent/KR100798667B1/ko
Pending legal-status Critical Current

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JP2004057598A 2004-03-02 2004-03-02 マルチレイヤシステム及びクロック制御方法 Pending JP2005250650A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2004057598A JP2005250650A (ja) 2004-03-02 2004-03-02 マルチレイヤシステム及びクロック制御方法
US11/068,753 US7277976B2 (en) 2004-03-02 2005-03-02 Multilayer system and clock control method
CNB2005100531069A CN1332282C (zh) 2004-03-02 2005-03-02 多层系统和时钟控制方法
KR1020050017456A KR20060043346A (ko) 2004-03-02 2005-03-02 다층 시스템 및 클럭 제어 방법
KR1020070032519A KR100798667B1 (ko) 2004-03-02 2007-04-02 다층 시스템 및 클럭 제어 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004057598A JP2005250650A (ja) 2004-03-02 2004-03-02 マルチレイヤシステム及びクロック制御方法

Publications (2)

Publication Number Publication Date
JP2005250650A JP2005250650A (ja) 2005-09-15
JP2005250650A5 true JP2005250650A5 (enExample) 2006-12-21

Family

ID=34909040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004057598A Pending JP2005250650A (ja) 2004-03-02 2004-03-02 マルチレイヤシステム及びクロック制御方法

Country Status (4)

Country Link
US (1) US7277976B2 (enExample)
JP (1) JP2005250650A (enExample)
KR (2) KR20060043346A (enExample)
CN (1) CN1332282C (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4477380B2 (ja) * 2004-03-02 2010-06-09 Ｎｅｃエレクトロニクス株式会社 マルチレイヤシステム及びクロック制御方法
JP2007183860A (ja) * 2006-01-10 2007-07-19 Nec Electronics Corp クロック制御回路
US8006021B1 (en) * 2008-03-27 2011-08-23 Xilinx, Inc. Processor local bus bridge for an embedded processor block core in an integrated circuit
KR100932868B1 (ko) * 2008-05-13 2009-12-21 (주)퓨처스코프테크놀러지 클락신호에 의하여 제어되는 반도체 장치의 테스트 모드회로 및 이의 구동방법
JP2010072897A (ja) 2008-09-18 2010-04-02 Nec Electronics Corp クロック供給装置
TWI461071B (zh) * 2008-12-08 2014-11-11 The Manufacturing Method of Composite Material Cantilever Type Chip Shock Absorber
US8255722B2 (en) * 2009-03-09 2012-08-28 Atmel Corporation Microcontroller with clock generator for supplying activated clock signal to requesting module to conserve power
JP5578811B2 (ja) 2009-06-30 2014-08-27 キヤノン株式会社 情報処理装置、情報処理装置の制御方法及びプログラム
US8704903B2 (en) * 2009-12-29 2014-04-22 Cognex Corporation Distributed vision system with multi-phase synchronization
GB201211340D0 (en) 2012-06-26 2012-08-08 Nordic Semiconductor Asa Control of semiconductor devices
CN105676944B (zh) * 2014-11-18 2019-03-26 龙芯中科技术有限公司 时钟网络的开关控制方法、装置及处理器

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5345564A (en) * 1992-03-31 1994-09-06 Zilog, Inc. Serial communication peripheral integrated electronic circuit that recognizes its unique address before the entire circuit is enabled
JPH06176875A (ja) * 1992-12-10 1994-06-24 Matsushita Electric Ind Co Ltd 住宅照明器具
US5600839A (en) * 1993-10-01 1997-02-04 Advanced Micro Devices, Inc. System and method for controlling assertion of a peripheral bus clock signal through a slave device
US6163848A (en) * 1993-09-22 2000-12-19 Advanced Micro Devices, Inc. System and method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus
DE4441752A1 (de) * 1994-11-23 1996-05-30 Siemens Ag Anordnung mit einer Master-Einheit und mehreren Slave-Einheiten
JP3710845B2 (ja) * 1995-06-21 2005-10-26 株式会社ルネサステクノロジ 半導体記憶装置
GB9625437D0 (en) * 1996-12-06 1997-01-22 Alpha Therm Limited Improvements in or relating to a clock arrangement
US20030093702A1 (en) * 2001-03-30 2003-05-15 Zheng Luo System on a chip with multiple power planes and associate power management methods
JP2003141061A (ja) 2001-11-01 2003-05-16 Nec Corp Ｉ２ｃバス制御方法及びｉ２ｃバスシステム
JP2003296296A (ja) * 2002-01-30 2003-10-17 Oki Electric Ind Co Ltd マイクロコントローラ
US7007181B2 (en) * 2002-04-23 2006-02-28 Oki Electric Industry Co., Ltd. Microcontroller
KR100591524B1 (ko) * 2004-05-14 2006-06-19 삼성전자주식회사 버스 구조하에서 다이나믹 클록 게이팅이 가능한 슬레이브장치 및 그 동작방법
JP4715602B2 (ja) * 2005-05-30 2011-07-06 トヨタ自動車株式会社 内燃機関の潤滑装置
KR100693610B1 (ko) * 2005-06-30 2007-03-14 현대자동차주식회사 엘피아이 엔진의 연료 공급 장치
JP4825598B2 (ja) * 2006-06-23 2011-11-30 株式会社ミツトヨ 画像測定装置の校正方法

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