CN1332282C - 多层系统和时钟控制方法 - Google Patents

多层系统和时钟控制方法 Download PDF

Info

Publication number
CN1332282C
CN1332282C CNB2005100531069A CN200510053106A CN1332282C CN 1332282 C CN1332282 C CN 1332282C CN B2005100531069 A CNB2005100531069 A CN B2005100531069A CN 200510053106 A CN200510053106 A CN 200510053106A CN 1332282 C CN1332282 C CN 1332282C
Authority
CN
China
Prior art keywords
module
clock
primary module
primary
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100531069A
Other languages
English (en)
Chinese (zh)
Other versions
CN1664744A (zh
Inventor
星幸子
成相恭一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1664744A publication Critical patent/CN1664744A/zh
Application granted granted Critical
Publication of CN1332282C publication Critical patent/CN1332282C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3237Power saving characterised by the action undertaken by disabling clock generation or distribution
    • DTEXTILES; PAPER
    • D06TREATMENT OF TEXTILES OR THE LIKE; LAUNDERING; FLEXIBLE MATERIALS NOT OTHERWISE PROVIDED FOR
    • D06HMARKING, INSPECTING, SEAMING OR SEVERING TEXTILE MATERIALS
    • D06H7/00Apparatus or processes for cutting, or otherwise severing, specially adapted for the cutting, or otherwise severing, of textile materials
    • D06H7/04Apparatus or processes for cutting, or otherwise severing, specially adapted for the cutting, or otherwise severing, of textile materials longitudinally
    • D06H7/06Removing selvedge edges
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B26HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26DCUTTING; DETAILS COMMON TO MACHINES FOR PERFORATING, PUNCHING, CUTTING-OUT, STAMPING-OUT OR SEVERING
    • B26D7/00Details of apparatus for cutting, cutting-out, stamping-out, punching, perforating, or severing by means other than cutting
    • B26D7/20Cutting beds
    • DTEXTILES; PAPER
    • D06TREATMENT OF TEXTILES OR THE LIKE; LAUNDERING; FLEXIBLE MATERIALS NOT OTHERWISE PROVIDED FOR
    • D06HMARKING, INSPECTING, SEAMING OR SEVERING TEXTILE MATERIALS
    • D06H7/00Apparatus or processes for cutting, or otherwise severing, specially adapted for the cutting, or otherwise severing, of textile materials
    • D06H7/22Severing by heat or by chemical agents
    • D06H7/221Severing by heat or by chemical agents by heat
    • D06H7/223Severing by heat or by chemical agents by heat using ultrasonic vibration
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038System on Chip
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Textile Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Forests & Forestry (AREA)
  • Mechanical Engineering (AREA)
  • Telephone Function (AREA)
  • Electronic Switches (AREA)
  • Power Sources (AREA)
CNB2005100531069A 2004-03-02 2005-03-02 多层系统和时钟控制方法 Expired - Fee Related CN1332282C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004057598 2004-03-02
JP2004057598A JP2005250650A (ja) 2004-03-02 2004-03-02 マルチレイヤシステム及びクロック制御方法

Publications (2)

Publication Number Publication Date
CN1664744A CN1664744A (zh) 2005-09-07
CN1332282C true CN1332282C (zh) 2007-08-15

Family

ID=34909040

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100531069A Expired - Fee Related CN1332282C (zh) 2004-03-02 2005-03-02 多层系统和时钟控制方法

Country Status (4)

Country Link
US (1) US7277976B2 (enExample)
JP (1) JP2005250650A (enExample)
KR (2) KR20060043346A (enExample)
CN (1) CN1332282C (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4477380B2 (ja) * 2004-03-02 2010-06-09 Necエレクトロニクス株式会社 マルチレイヤシステム及びクロック制御方法
JP2007183860A (ja) * 2006-01-10 2007-07-19 Nec Electronics Corp クロック制御回路
US8006021B1 (en) * 2008-03-27 2011-08-23 Xilinx, Inc. Processor local bus bridge for an embedded processor block core in an integrated circuit
KR100932868B1 (ko) * 2008-05-13 2009-12-21 (주)퓨처스코프테크놀러지 클락신호에 의하여 제어되는 반도체 장치의 테스트 모드회로 및 이의 구동방법
JP2010072897A (ja) 2008-09-18 2010-04-02 Nec Electronics Corp クロック供給装置
TWI461071B (zh) * 2008-12-08 2014-11-11 The Manufacturing Method of Composite Material Cantilever Type Chip Shock Absorber
US8255722B2 (en) * 2009-03-09 2012-08-28 Atmel Corporation Microcontroller with clock generator for supplying activated clock signal to requesting module to conserve power
JP5578811B2 (ja) 2009-06-30 2014-08-27 キヤノン株式会社 情報処理装置、情報処理装置の制御方法及びプログラム
US8704903B2 (en) * 2009-12-29 2014-04-22 Cognex Corporation Distributed vision system with multi-phase synchronization
GB201211340D0 (en) 2012-06-26 2012-08-08 Nordic Semiconductor Asa Control of semiconductor devices
CN105676944B (zh) * 2014-11-18 2019-03-26 龙芯中科技术有限公司 时钟网络的开关控制方法、装置及处理器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06176875A (ja) * 1992-12-10 1994-06-24 Matsushita Electric Ind Co Ltd 住宅照明器具
WO1996016370A1 (de) * 1994-11-23 1996-05-30 Siemens Aktiengesellschaft Anordnung mit einer master-einheit und mehreren slave-einheiten
JPH097396A (ja) * 1995-06-21 1997-01-10 Mitsubishi Electric Corp 半導体記憶装置、そのデータ書込方法およびその並列試験装置
EP0846990A1 (en) * 1996-12-06 1998-06-10 Alpha Therm Ltd. A time clock arrangement

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5345564A (en) * 1992-03-31 1994-09-06 Zilog, Inc. Serial communication peripheral integrated electronic circuit that recognizes its unique address before the entire circuit is enabled
US5600839A (en) * 1993-10-01 1997-02-04 Advanced Micro Devices, Inc. System and method for controlling assertion of a peripheral bus clock signal through a slave device
US6163848A (en) * 1993-09-22 2000-12-19 Advanced Micro Devices, Inc. System and method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus
US20030093702A1 (en) * 2001-03-30 2003-05-15 Zheng Luo System on a chip with multiple power planes and associate power management methods
JP2003141061A (ja) 2001-11-01 2003-05-16 Nec Corp I2cバス制御方法及びi2cバスシステム
JP2003296296A (ja) * 2002-01-30 2003-10-17 Oki Electric Ind Co Ltd マイクロコントローラ
US7007181B2 (en) * 2002-04-23 2006-02-28 Oki Electric Industry Co., Ltd. Microcontroller
KR100591524B1 (ko) * 2004-05-14 2006-06-19 삼성전자주식회사 버스 구조하에서 다이나믹 클록 게이팅이 가능한 슬레이브장치 및 그 동작방법
JP4715602B2 (ja) * 2005-05-30 2011-07-06 トヨタ自動車株式会社 内燃機関の潤滑装置
KR100693610B1 (ko) * 2005-06-30 2007-03-14 현대자동차주식회사 엘피아이 엔진의 연료 공급 장치
JP4825598B2 (ja) * 2006-06-23 2011-11-30 株式会社ミツトヨ 画像測定装置の校正方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06176875A (ja) * 1992-12-10 1994-06-24 Matsushita Electric Ind Co Ltd 住宅照明器具
WO1996016370A1 (de) * 1994-11-23 1996-05-30 Siemens Aktiengesellschaft Anordnung mit einer master-einheit und mehreren slave-einheiten
JPH097396A (ja) * 1995-06-21 1997-01-10 Mitsubishi Electric Corp 半導体記憶装置、そのデータ書込方法およびその並列試験装置
US6301166B1 (en) * 1995-06-21 2001-10-09 Mitsubishi Denki Kabushiki Kaisha Parallel tester capable of high speed plural parallel test
EP0846990A1 (en) * 1996-12-06 1998-06-10 Alpha Therm Ltd. A time clock arrangement

Also Published As

Publication number Publication date
KR20070045162A (ko) 2007-05-02
KR20060043346A (ko) 2006-05-15
KR100798667B1 (ko) 2008-01-28
US20050198418A1 (en) 2005-09-08
JP2005250650A (ja) 2005-09-15
US7277976B2 (en) 2007-10-02
CN1664744A (zh) 2005-09-07

Similar Documents

Publication Publication Date Title
KR100798667B1 (ko) 다층 시스템 및 클럭 제어 방법
US6745369B1 (en) Bus architecture for system on a chip
US20050273526A1 (en) Data processing system and data processor
US7725621B2 (en) Semiconductor device and data transfer method
CN1945741B (zh) 半导体存储装置及具备该半导体存储装置的收发系统
JP2002351737A (ja) 半導体記憶装置
JP3665030B2 (ja) バス制御方法及び情報処理装置
JP4902640B2 (ja) 集積回路、及び集積回路システム
JPH10143466A (ja) バス通信システム
CN114996184B (zh) 兼容实现spi或i2c从机的接口模块及数据传输方法
JPH11202968A (ja) マイクロコンピュータ
JP2001034530A (ja) マイクロコンピュータおよびメモリアクセス制御方法
KR100700158B1 (ko) 다층시스템 및 클록제어방법
JP2009075973A (ja) 電子機器及び当該電子機器の電力制御方法
JP4480661B2 (ja) 半導体集積回路装置
JP2004199115A (ja) 半導体集積回路
JP6128833B2 (ja) 処理装置
JP2005010638A (ja) ディスプレイ制御装置およびディスプレイ制御方法
JP2010128793A (ja) バスクロック制御装置とその制御方法とメモリカードコントローラ
JPH11306073A (ja) 情報処理装置
JP2002007310A (ja) 半導体装置
JPH0962612A (ja) Dma制御方法及びdmaコントローラ
JPH10105288A (ja) データ処理システムおよび柔軟なリセット設定方法
JP2004234269A (ja) データ転送装置
JP2007199904A (ja) 情報処理装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: RENESAS ELECTRONICS CO., LTD.

Free format text: FORMER OWNER: NEC CORP.

Effective date: 20101119

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20101119

Address after: Kanagawa, Japan

Patentee after: Renesas Electronics Corporation

Address before: Kanagawa, Japan

Patentee before: NEC Corp.

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070815

Termination date: 20140302