JP2005175434A5 - - Google Patents

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Publication number
JP2005175434A5
JP2005175434A5 JP2004283352A JP2004283352A JP2005175434A5 JP 2005175434 A5 JP2005175434 A5 JP 2005175434A5 JP 2004283352 A JP2004283352 A JP 2004283352A JP 2004283352 A JP2004283352 A JP 2004283352A JP 2005175434 A5 JP2005175434 A5 JP 2005175434A5
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JP
Japan
Prior art keywords
conductive
forming
dielectric layer
integrated circuit
runner
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Granted
Application number
JP2004283352A
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English (en)
Japanese (ja)
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JP2005175434A (ja
JP4948756B2 (ja
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Publication of JP2005175434A publication Critical patent/JP2005175434A/ja
Publication of JP2005175434A5 publication Critical patent/JP2005175434A5/ja
Application granted granted Critical
Publication of JP4948756B2 publication Critical patent/JP4948756B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2004283352A 2003-09-30 2004-09-29 集積回路内に形成されたインダクタ及びその製造方法 Expired - Lifetime JP4948756B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US50733503P 2003-09-30 2003-09-30
US60/507335 2003-09-30

Publications (3)

Publication Number Publication Date
JP2005175434A JP2005175434A (ja) 2005-06-30
JP2005175434A5 true JP2005175434A5 (https=) 2007-10-18
JP4948756B2 JP4948756B2 (ja) 2012-06-06

Family

ID=33418512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004283352A Expired - Lifetime JP4948756B2 (ja) 2003-09-30 2004-09-29 集積回路内に形成されたインダクタ及びその製造方法

Country Status (5)

Country Link
US (3) US7068139B2 (https=)
JP (1) JP4948756B2 (https=)
KR (1) KR101045195B1 (https=)
GB (1) GB2406720B (https=)
TW (1) TWI362098B (https=)

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US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
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US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
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US8859419B2 (en) 2013-02-01 2014-10-14 Globalfoundries Inc. Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
US9263405B2 (en) * 2013-12-05 2016-02-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device
US10032850B2 (en) * 2016-05-11 2018-07-24 Texas Instruments Incorporated Semiconductor die with back-side integrated inductive component
US10263064B2 (en) * 2017-06-30 2019-04-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of forming the same
US11495555B2 (en) * 2018-03-14 2022-11-08 Intel Corporation Magnetic bilayer structure for a cored or coreless semiconductor package
US11270959B2 (en) * 2018-03-23 2022-03-08 Intel Corporation Enabling magnetic films in inductors integrated into semiconductor packages
US11355459B2 (en) * 2018-05-17 2022-06-07 Intel Corpoation Embedding magnetic material, in a cored or coreless semiconductor package
US10748810B2 (en) 2018-05-29 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing an integrated inductor with protections caps on conductive lines
US10756161B2 (en) * 2018-06-27 2020-08-25 Intel Corporation Package-embedded thin-film capacitors, package-integral magnetic inductors, and methods of assembling same
US11049820B2 (en) * 2018-07-30 2021-06-29 Texas Instruments Incorporated Crack suppression structure for HV isolation component
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