JP2005123291A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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JP2005123291A
JP2005123291A JP2003354680A JP2003354680A JP2005123291A JP 2005123291 A JP2005123291 A JP 2005123291A JP 2003354680 A JP2003354680 A JP 2003354680A JP 2003354680 A JP2003354680 A JP 2003354680A JP 2005123291 A JP2005123291 A JP 2005123291A
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columnar electrode
burn
semiconductor device
sealing film
semiconductor substrate
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JP3757971B2 (ja
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Takeshi Wakabayashi
猛 若林
Ichiro Mihara
一郎 三原
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Priority to JP2003354680A priority Critical patent/JP3757971B2/ja
Priority to CNB2004100951516A priority patent/CN1329970C/zh
Priority to US10/964,019 priority patent/US20050084989A1/en
Priority to KR1020040081598A priority patent/KR20050036743A/ko
Priority to TW093131075A priority patent/TWI248149B/zh
Publication of JP2005123291A publication Critical patent/JP2005123291A/ja
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Abstract

【課題】 半田ボールを備えた半導体装置において、プローブピンを半田ボールに接触させずにバーンインを行なう。
【解決手段】 ウエハ状態の半導体基板１上に柱状電極９および封止膜１０を形成した後に、柱状電極１０上にプロープピン２３を接触させてバーンインを行なう。次に、柱状電極１０上に半田ボールを形成し、ウエハ状態の半導体基板１をダイシングする。この結果、プローブピン２３の接触による半田ボールの不要な変形を防止することができ、また、半田ボールの高さにばらつきがあっても、バーンインを行なうことができる。
【選択図】 図６

Description

この発明は半導体装置の製造方法に関する。
ＬＳＩ等の半導体技術の分野では、信頼性を保証するために、バーンインを行なっている。従来では、個片化された半導体装置に対してバーンインを行なっている。（例えば、特許文献１参照）。しかしながら、この場合、個片化された半導体装置に対してバーンインを行なうため、非能率的である。
特開２００３−２８２８１４号公報
一方、半導体装置には、一般的にＣＳＰ(chip size package)と呼ばれるもので、複数の接続パッドを有する半導体基板の上面に絶縁膜が設けられ、絶縁膜の接続パッドに対応する部分に開口部が設けられ、絶縁膜の上面に再配線が開口部を介して接続パッドに接続されて設けられ、再配線の接続パッド部上面に柱状電極が設けられ、再配線を含む絶縁膜の上面に封止膜がその上面が柱状電極の上面と面一となるように設けられ、柱状電極の上面に半田ボールが設けられたものがある（例えば、特許文献２参照）。
特開２００２−２３１８５４号公報
ところで、特許文献２に記載のような半田ボールを備えた半導体装置に対してバーンインを行なう場合には、半田ボールにプローブピンを接触させることになる。しかしながら、プローブピンを比較的軟らかな半田ボールに接触させると、半田ボールが変形することがあり、この変形に起因して、位置合わせ用カメラによる半田ボールの位置認識に誤認が生じ、半導体装置を回路基板上に接合するとき、位置合わせ不良が生じ、ひいては、接合不良が発生することがあった。また、半田ボールの凹みにより半導体装置の半田ボールの高さにばらつきが生じるため、プローブピンの半田ボールへの接触不良が発生し、適切なバーンインが行われないものも生じた。
そこで、この発明は、半田ボールを変形させることなくバーンインを行なうことができ、以って、バーンインを確実に行い且つ接合の信頼性を向上することができる半導体装置の製造方法を提供することを目的とする。
請求項１に記載の発明は、半導体基板上に柱状電極が設けられ、前記柱状電極の周囲における前記半導体基板上に封止膜が設けられ、前記柱状電極上に半田ボールが設けられた半導体装置の製造方法において、ウエハ状態の半導体基板上に前記柱状電極および前記封止膜を形成した後に、前記柱状電極上にプロープピンを接触させてバーンインを行ない、次いで、前記柱状電極上に半田ボールを形成し、前記ウエハ状態の半導体基板をダイシングすることを特徴とするものである。
請求項２に記載の発明は、請求項１に記載の発明において、前記柱状電極を形成した後に、前記柱状電極の上面を覆うように前記封止膜を形成し、前記封止膜の上面側を研磨して前記柱状電極の上面を露出させ、前記柱状電極の上面側をエッチングし、この後、前記バーンインを行なうことを特徴とするものである。
請求項３に記載の発明は、請求項１または２に記載の発明において、前記バーンインを行なった後に、前記柱状電極の上面が前記封止膜の上面より低くなるようにエッチングし、次いで、前記柱状電極上に前記半田ボールを形成することを特徴とするものである。
請求項４に記載の発明は、請求項２に記載の発明において、前記柱状電極の上面側をエッチングした後に、前記柱状電極の上面に表面処理層を形成し、この後、前記バーンインを行なうことを特徴とするものである。
請求項５に記載の発明は、請求項４に記載の発明において、前記表面処理層の上面を前記封止膜の上面よりも低くすることを特徴とするものである。
この発明によれば、ウエハ状態の半導体基板に対して、半田ボールを形成する前に、柱状電極上にプロープピンを接触させてバーンインを行なっているので、プローブピンの接触による半田ボールの不要な変形を防止することができ、この結果、バーンインを確実に行い且つ接合の信頼性を向上することができる。
図１はこの発明の一実施形態としての製造方法により製造された半導体装置の断面図を示す。この半導体装置は、シリコン等からなる半導体基板１を備えている。半導体基板１の上面には所定の機能の集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッド２が集積回路に接続されて設けられている。接続パッド２の中央部を除く半導体基板１の上面には酸化シリコン等からなる絶縁膜３が設けられ、接続パッド２の中央部は絶縁膜３に設けられた開口部４を介して露出されている。
絶縁膜３の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる保護膜（絶縁膜）５が設けられている。この場合、絶縁膜３の開口部４に対応する部分における保護膜５には開口部６が設けられている。保護膜５の上面には銅等からなる下地金属層７が設けられている。下地金属層７の上面全体には銅からなる再配線８が設けられている。下地金属層７を含む再配線８の一端部は、両開口部４、６を介して接続パッド２に接続されている。
再配線８の接続パッド部上面には銅からなる柱状電極９が設けられている。再配線８を含む保護膜５の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる封止膜１０がその上面が柱状電極９の上面よりも高くなるように設けられている。したがって、柱状電極９上における封止膜１０には開口部１１が設けられている。開口部１１内およびその上側には半田ボール１２が柱状電極９の上面に接続されて設けられている。
次に、この半導体装置の製造方法の一例について説明する。まず、図２に示すように、ウエハ状態の半導体基板１の上面に接続パッド２が形成され、その上面に絶縁膜３および保護膜５が形成され、その上面に下地金属層７を含む再配線８が絶縁膜３および保護膜５に形成された開口部４、６を介して接続パッド２に接続されて形成され、再配線８の接続パッド部上面に柱状電極９が形成されたものを用意する。
次に、図３に示すように、スクリーン印刷法、スピンコーティング法、ダイコート法等により、柱状電極９および再配線８を含む保護膜５の上面全体にエポキシ系樹脂等からなる封止膜１０をその厚さが柱状電極９の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極９の上面は封止膜１０によって覆われている。
次に、封止膜１０および柱状電極９の上面側を適宜に研磨し、図４に示すように、柱状電極９の上面を露出させるとともに、この露出された柱状電極９の上面を含む封止膜１０の上面を平坦化する。ここで、柱状電極９の上面側を適宜に研磨するのは、電解メッキにより形成される柱状電極９の高さにばらつきがあるため、このばらつきを解消して、柱状電極９の高さを均一にするためである。
次に、図５に示すように、ハーフエッチングにより、柱状電極９の上面側をやや一例として５μｍ程度除去し、柱状電極９上における封止膜１０に開口部１１を形成する。この場合、柱状電極９に対するハーフエッチングはほぼ均等に行なわれ、且つ、エッチング量は５μｍ程度と極めて小さいため、開口部１０の深さはほぼ均一となる。
次に、図６に示すように、バーンイン用検査治具２１として、下面に配線（図示せず）を有する配線基板２２の下面側に複数のプローブピン２３を有するプローブピン支持板２４が配置され、プローブピン２３の上端面が異方導電性ゴム２５を介して配線基板２２の配線に接続されたものを用意する。この場合、プローブピン２３の先端部はほぼ半球形状となっている。また、プローブピン２３の直径は封止膜１０の開口部１１の直径よりもある程度小さくなっている。
そして、図示しないステージ上に配置されたウエハ状態の半導体基板１の封止膜１０の開口部１１内における柱状電極９の上面に、バーンイン用検査治具２１のプローブピン２３の先端部を接触させ、バーンインを行なう。この場合、封止膜１０の開口部１１の深さはほぼ均一となっているため、開口部１１内における柱状電極９の上面にプローブピン２３の先端部を確実に接触させることができ、電気的接続不良を確実に防止することができる。
また、プローブピン２３の直径は封止膜１０の開口部１１の直径よりもある程度小さくなっているため、プローブピン２３の開口部１１に対する位置合わせが多少ずれても、プローブピン２３の先端部を開口部１１内に確実に配置することができる。さらに、測定中にプローブピン２３が多少スライドしても開口部１１の内壁面に当接するため、プローブピン２３の先端部の柱状電極９の上面に対する電気的接触を確実に維持することができる。
そして、バーンインが終了したら、次に、図７に示すように、封止膜１０の開口部１１内およびその上側に半田ボール１２を柱状電極９の上面に接続させて形成する。次に、半導体基板１の下面をダイシングテープ（図示せず）に貼り付け、図８に示すダイシング工程を経た後に、ダイシングテープから剥がすと、図１に示す半導体装置が複数個得られる。
以上のように、上記半導体装置の製造方法では、半田ボール１２を形成する前に、柱状電極９上にプロープピン２３を接触させてバーンインを行なっているので、プローブピン２３を半田ボール１２に接触させずにバーンインを行なうことができる。この結果、半田ボール１２の不要な変形を防止することができ、また、半田ボール１２の高さにばらつきがあっても、バーンインを行なうことができる。さらに、ウエハ状態の半導体基板１に対してバーンインを行なっているので、能率的である。
なお、図６に示すバーンインを行なった後に、柱状電極９の上面に形成された自然酸化膜をソフトエッチングして除去し、次いで、柱状電極９の上面に半田ボール１２を形成するようにしてもよい。また、図５に示す工程後に、ニッケル／金、ニッケル／半田、ニッケル／錫等の無電解メッキを行なうことにより、柱状電極９の上面に酸化防止用の表面処理層を形成し、この後、バーンインを行なうようにしてもよい。この場合、表面処理層の上面を封止膜１０の上面よりもやや低くし、表面処理層上における封止膜１０に開口部１１が残存されるようにしてもよい。さらに、図４に示す工程後に、バーンインを行ない、次いで、柱状電極９の上面側をハーフエッチングせずに、封止膜１０の上面と面一の柱状電極９の上面に半田ボール１２を形成するようにしてもよい。
この発明の一実施形態としての製造方法により製造された半導体装置の断面図。 図１に示す半導体装置の製造に際し、当初用意したものの断面図。 図２に続く工程の断面図。 図３に続く工程の断面図。 図４に続く工程の断面図。 図５に続く工程の断面図。 図６に続く工程の断面図。 図７に続く工程の断面図。
符号の説明
１ 半導体基板
２ 接続パッド
３ 絶縁膜
５ 保護膜
８ 再配線
９ 柱状電極
１０ 封止膜
１１ 開口部
１２ 半田ボール
２１ バーンイン用検査治具
２３ プローブピン

Claims (5)

  1. 半導体基板上に柱状電極が設けられ、前記柱状電極の周囲における前記半導体基板上に封止膜が設けられ、前記柱状電極上に半田ボールが設けられた半導体装置の製造方法において、ウエハ状態の半導体基板上に前記柱状電極および前記封止膜を形成した後に、前記柱状電極上にプロープピンを接触させてバーンインを行ない、次いで、前記柱状電極上に半田ボールを形成し、前記ウエハ状態の半導体基板をダイシングすることを特徴とする半導体装置の製造方法。
  2. 請求項１に記載の発明において、前記柱状電極を形成した後に、前記柱状電極の上面を覆うように前記封止膜を形成し、前記封止膜の上面側を研磨して前記柱状電極の上面を露出させ、前記柱状電極の上面側をエッチングし、この後、前記バーンインを行なうことを特徴とする半導体装置の製造方法。
  3. 請求項１または２に記載の発明において、前記バーンインを行なった後に、前記柱状電極の上面が前記封止膜の上面より低くなるようにエッチングし、次いで、前記柱状電極上に前記半田ボールを形成することを特徴とする半導体装置の製造方法。
  4. 請求項２に記載の発明において、前記柱状電極の上面側をエッチングした後に、前記柱状電極の上面に表面処理層を形成し、この後、前記バーンインを行なうことを特徴とする半導体装置の製造方法。
  5. 請求項４に記載の発明において、前記表面処理層の上面を前記封止膜の上面よりも低くすることを特徴とする半導体装置の製造方法。
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JP2010199384A (ja) * 2009-02-26 2010-09-09 Oki Semiconductor Co Ltd 半導体チップの電気特性測定方法
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