JP2005079310A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2005079310A JP2005079310A JP2003307148A JP2003307148A JP2005079310A JP 2005079310 A JP2005079310 A JP 2005079310A JP 2003307148 A JP2003307148 A JP 2003307148A JP 2003307148 A JP2003307148 A JP 2003307148A JP 2005079310 A JP2005079310 A JP 2005079310A
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Abstract
【解決手段】 シリコン基板2上にゲート絶縁膜6を介してSiGe膜10を含むゲート電極を有する半導体装置であって、ゲート絶縁膜6は、下地界面層6aと、下地界面層6aよりも高い比誘電率を有する高誘電体膜6bとを含み、ゲート電極は、高誘電体膜6b上に形成されたシードSi膜8と、シードSi膜8上に形成されたSiGe膜10とを含む。シードSi膜8の膜厚は、0.1nm以上5nm未満である。
【選択図】 図1
Description
しかし、このような極薄のSiO2膜をゲート絶縁膜として用いた場合、トンネル電流によるゲート漏れ電流がソース/ドレイン電流に対して無視できない値となり、MOSFETの高性能化と低消費電力化において大きな課題となっている。
この課題に対して、SiO2膜よりも高い比誘電率を有する高誘電体膜(「High−k膜」ともいう。)をゲート絶縁膜として用いる方法が検討されている。高誘電体膜の材料としては、例えば、HfO2、ZrO2、Al2O3のような金属酸化物、HfSiOx、ZrSiOzのような金属シリケート、HfAlOx、ZrAlOxのような金属アルミネート、La2O3、Y2O3のようなランタノイド系元素の酸化物等が挙げられる。特に、Hfを構成元素として含むハフニア膜(HfO2膜)、Hfアルミネート膜(HfAlOx膜)又はHfシリケート膜(HfSiOx膜)、或いはアルミナ膜(Al2O3膜)、或いはこれらを窒化処理した膜は、良好な熱的安定性を有するため、LSI製造プロセスへの導入が比較的容易であると考えられている。
これらの高誘電体膜の比誘電率は6以上であり、SiO2膜の比誘電率3.9よりも高い。よって、ゲート絶縁膜の実効的な膜厚、すなわち、電気的換算膜厚(Equivalent Oxide Thickness、以下「EOT」という。)を薄くしたままで、物理的膜厚を厚くすることができる。このため、トンネル電流によるゲート漏れ電流を抑えることができる。
さらに、高誘電体膜をゲート絶縁膜として用いた場合には、シリコン酸化膜(SiO2膜)やシリコン酸窒化膜(SiON膜)をゲート絶縁膜として用いた場合と比較して、SiGe膜の膜不良の発生の仕方が異なることが、本発明者等の独自の調査により分かった。以下に、膜不良の具体例を示す。
また、図6に示すように、高誘電体膜とSiGe膜との間に5nm以上の膜厚でシードSi膜を介在させた場合には、SiGe膜中でボイド(図中の丸印で示す部分)が発生してしまうことが分かった。
前記ゲート絶縁膜は、下地界面層と、該下地界面層よりも高い比誘電率を有する高誘電体膜とを含み、
前記ゲート電極は、前記高誘電体膜上に形成されたシードSi膜と、該シードSi膜上に形成されたSiGe膜とを含むことを特徴とするものである。
さらに、前記ゲート電極は、前記下部キャップSi膜上に形成された上部キャップSi膜と、該上部キャップSi膜の上層に形成された金属シリサイド層とを更に含むことが好適である。
また、前記高誘電体膜は、HfSiOx膜又はAl2O3膜、或いはそれらを窒化処理した膜であることが好適である。
前記高誘電体膜上にシードSi膜を形成する工程と、
前記シードSi膜上にSiGe膜を形成する工程と、
前記SiGe膜及び前記シードSi膜をパターニングしてゲート電極を形成した後、前記高誘電体膜をパターニングする工程と、
前記ゲート電極をマスクとしたイオン注入により前記基板の上層に不純物拡散層を形成する工程と、
を含むことを特徴とするものである。
前記不純物拡散層を形成した後、前記上部キャップSi膜及び前記不純物拡散層の上層に金属シリサイド層を形成する工程を含むことが好適である。
先ず、本発明の実施の形態1による半導体装置の構造について説明する。
図1は、本発明の実施の形態1による半導体装置を説明するための断面図である。
図1に示すように、基板2としてのシリコン基板には、トランジスタのような半導体素子が形成される素子領域と、この素子領域を分離する分離領域とがあり、該分離領域にフィールド絶縁膜(「素子分離絶縁膜」ともいう。)4が形成されている。また、図示しないが、素子領域のシリコン基板2内には、ウェル領域が形成されている。
下地界面層6aとしては、例えば、SiO2膜、Si3N4膜、SiON膜又はそれらの積層膜(以下「SiO2膜等」という。)を用いることができる。下地界面層6aの膜厚は、例えば、0.5nm−1nmである。下地界面層6aは、シリコン基板2と高誘電体膜6bとの界面反応を抑制するために形成されるものである。
高誘電体膜6bとしては、例えば、Hf組成が50%未満であるHfアルミネート膜(HfAlOx膜)、或いはHfシリケート膜(HfSiOx膜)、Al2O3膜、或いはこれらを窒化処理した膜を用いることができる。これらの高誘電体膜6bの比誘電率は6以上であり、その膜厚は、例えば、2nm−3nmである。
シードSi膜8上には、下部電極膜としてのSiGe膜10が形成されている。SiGe膜10の膜厚は、例えば、50nm以下が好適である。SiGe膜10は、Si(100−y)Geyなる組成式で表されるが、Ge組成Y(%)は、15%以上40%未満が好適であり、30%程度が更に好適である(後述)。また、SiGe膜10は、450℃以上500℃未満の温度で成長させたものが好適であり、475℃の温度で成長させたものが更に好適である(後述)。
ゲート電極下方のチャネル領域(図示省略)を挟んで、シリコン基板2の上層にエクステンション領域14が形成され、このエクステンション領域14に接続するソース/ドレイン領域18が形成されている。
上部キャップSi膜12b及びソース/ドレイン領域18の上層には、金属シリサイド層20としてのNiシリサイド層が形成されている。すなわち、本実施の形態におけるMOSトランジスタはサリサイド構造を有する。
図2は、図1に示した半導体装置の製造方法を説明するための工程断面図である。
先ず、図2(a)に示すように、シリコン基板2の分離領域に、STI(Shallow Trench Isolation)技術を用いて、フィールド絶縁膜4を形成する。そして、図示しないが、シリコン基板2の素子領域に導電型不純物のイオン注入を行い、さらにアニール処理を行うことによって、ウェル領域を形成する。
続いて、下地界面層6a上に、下地界面層6aより比誘電率が高い高誘電体膜6bを、ALD(Atomic Layer Deposition)法やMOCVD(Metal Organic Chemical Vapor Deposition)法を用いて形成する。例えば、ALD法によりHfAlOx膜を形成する場合、HfCl4及びTMAを原料とし、H2O又はO3を酸化剤とし、基板温度を300℃とするプロセス条件を用いることができる。
これにより、シリコン基板2上に、下地界面層6aと高誘電体膜6bとを積層してなるゲート絶縁膜6が形成される。
図3は、高誘電体膜上にシードSi膜を介してSiGe膜とキャップSi膜とからなる積層膜を形成した場合の、トランジスタの電気的特性を示す図である。詳細には、図3(a)は、シードSi膜の膜厚と、容量特性(C−V特性)から得られた電気的膜厚(EOT)との関係を示す図である。図3(b)は、シードSi膜の膜厚と、容量特性(C−V特性)から得られたSiGe膜の空乏化率との関係を示す図である。
上述した図3(a),(b)の調査結果より、シードSi膜の膜厚は、0.1nm以上5nm未満にすることが好適である。
ここで、Si(100−y)Geyの組成式で表されるSiGe膜10中のGe組成Y(%)は、15%以上40%未満とするのが好適であり、30%とするのが最も好適である。これは、ゲート電極材料としてSiGe膜を用いることによって得られるPMOSの電気的特性改善効果がGe組成15%未満では不十分であり、Ge組成30%以上で飽和するためである。また、Ge組成40%以上の場合には、NMOSの電気的特性が劣化する傾向が見られるためである。
また、SiGe膜10の成長温度は、450℃以上500℃未満が好適であり、475℃が最も好適である。これは、成長温度が500℃以上の場合には、SiGe膜の表面荒れが著しくなるためである。一方、成長温度が450℃未満の場合には、成膜レートが遅くなり、スループットが悪くなるためである。
例えば、バッチ式の縦型LPCVD装置を用いて、SiH4流量:0.6slm;H2希釈10%GeH4流量:0.58slm;温度:475℃;圧力:10Paのプロセス条件を用いることができる。なお、この条件により、優れた面内均一性と表面平坦性を有し、Ge濃度30%のSiGe膜を40nm程度の膜厚で形成できる。
例えば、バッチ式の縦型LPCVD装置を用いて、SiH4流量:1slm;温度:475℃;圧力:100Paの条件を用いて、下部キャップSi膜12aを約5nmの膜厚で形成することでできる。さらに、例えば、SiH4流量:0.6slm;温度:620℃;圧力:20Paの条件を用いて、上部キャップSi膜12bを約110nmの膜厚で形成することでできる。
キャップSi膜12のうち下部キャップSi膜12aをSiGe膜10と同じ膜形態で形成することにより、上部キャップSi膜12b形成時のSiGe膜10の膜形態変化を抑えることができ、SiGe膜10におけるボイド等の膜不良の発生を抑えることができる。これは、下部キャップSi膜12aによりSiGe膜10の表面エネルギーが下がり、SiGe膜10が安定化するためである。また、SiGe膜10上にキャップSi膜12を形成することにより、後述する金属シリサイド層20を安定して形成することができる。
図4(a)〜(c)に示すように、何れの高誘電体膜を用いた場合でもシードSi膜を介してSiGe膜を形成することにより、シードSi膜無しでSiGe膜を形成した場合(図5参照)に見られたようなSiGe膜のアイランド状の膜形態は観察されず、良好な膜形態のSiGe膜が得られることが分かった。また、従来図6で見られたようなボイドも観察されなかった。本発明者等は、シードSi膜の膜厚が0.1nm以上5nm以下の場合に、アイランド状の膜形態は観察されず、またボイドも観察されないことを確認した。よって、高誘電体膜を含むゲート絶縁膜に対して、シードSi膜の最適な膜厚の範囲を示唆している。
そして、パターニングされたゲート電極及びゲート絶縁膜6をマスクとして、シリコン基板2内に導電型不純物を注入した後、熱処理を行う。これにより、シリコン基板2上層にエクステンション領域14が形成される。
そして、ゲート電極、ゲート絶縁膜6及びサイドウォール16をマスクとして、シリコン基板2内に導電型不純物を注入した後、熱処理を行う。これにより、シリコン基板2上層に、エクステンション領域14と接続するソース/ドレイン領域18が形成される。
詳細には、希HF等を用いて所定の前洗浄を行った後、Ni膜を約10nmの膜厚で形成し、その上にTiN膜を約10nmの膜厚で形成する。その後、500℃程度の温度で熱処理を約30秒行い、未反応金属を除去することにより、金属シリサイド層20としてのNiシリサイド層が形成される。
また、SiGe膜10を形成した後、SiGe膜10と同一の成膜温度で連続して下部キャップSi膜12aを形成した。これにより、SiGe膜10と下部キャップSi膜10aとからなる連続膜構造を高誘電体膜6b上に形成することができる。
従って、ゲート電極/ゲート絶縁膜の界面におけるGe組成の均一性を改善することができ、局所的な界面Ge組成のバラツキによるトランジスタの閾値電圧のバラツキを抑制することができる。よって、素子バラツキが改善されるため、高性能なトランジスタを歩留まり良く作製することができ、生産性が向上する。
また、SiGe膜をゲート電極材料に用いることで、空乏化を抑制することができると共に、ゲート絶縁膜の薄膜化が可能となるため、より高性能なトランジスタを安価で且つ容易に作製することが可能となる。
さらに、SiGe膜10はボイドの無い良好な膜厚均一性を有する薄膜であるため、ゲート電極形成のドライエッチングにおいて、SiGe膜中のボイドに起因するシリコン基板2掘れ等の局所的な加工不良が回避できる。これにより、ゲート加工におけるプロセスマージンを拡大させることができ、高性能なトランジスタを安定して製造することができる。
4 フィールド絶縁膜(素子分離絶縁膜)
6 ゲート絶縁膜
6a 下地界面層
6b 高誘電体膜
8 シードSi膜
10 SiGe膜
12 キャップSi膜
12a 下部キャップSi膜
12b 上部キャップSi膜
14 エクステンション領域
16 サイドウォール
18 ソース/ドレイン領域
20 金属シリサイド層(Niシリサイド層)
Claims (12)
- 基板上にゲート絶縁膜を介して形成されたSiGe膜を含むゲート電極を有する半導体装置であって、
前記ゲート絶縁膜は、下地界面層と、該下地界面層よりも高い比誘電率を有する高誘電体膜とを含み、
前記ゲート電極は、前記高誘電体膜上に形成されたシードSi膜と、該シードSi膜上に形成されたSiGe膜とを含むことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記ゲート電極は、前記SiGe膜上に形成され、前記SiGe膜と同じ膜形態を有する下部キャップSi膜を更に含むことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記ゲート電極は、前記下部キャップSi膜上に形成された上部キャップSi膜と、該上部キャップSi膜の上層に形成された金属シリサイド層とを更に含むことを特徴とする半導体装置。 - 請求項1から3の何れかに記載の半導体装置において、
前記高誘電体膜は、Hf組成が50%未満であるHfAlOx膜、或いはそのHfAlOx膜を窒化処理した膜であることを特徴とする半導体装置。 - 請求項1から3の何れかに記載の半導体装置において、
前記高誘電体膜は、HfSiOx膜又はAl2O3膜、或いはそれらを窒化処理した膜であることを特徴とする半導体装置。 - 請求項1から5の何れかに記載の半導体装置において、
前記シードSi膜の膜厚が、0.1nm以上5nm未満であることを特徴とする半導体装置。 - 請求項1から6の何れかに記載の半導体装置において、
前記SiGe膜中のGe組成が、15%以上40%未満であることを特徴とする半導体装置。 - 請求項1から7の何れかに記載の半導体装置において、
前記SiGe膜の膜厚が50nm以下であることを特徴とする半導体装置。 - 基板上にゲート絶縁膜として高誘電体膜を形成する工程と、
前記高誘電体膜上にシードSi膜を形成する工程と、
前記シードSi膜上にSiGe膜を形成する工程と、
前記SiGe膜及び前記シードSi膜をパターニングしてゲート電極を形成した後、前記高誘電体膜をパターニングする工程と、
前記ゲート電極をマスクとしたイオン注入により前記基板の上層に不純物拡散層を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、
前記SiGe膜を形成した後、前記SiGe膜の形成温度と同じ温度で連続して前記SiGe膜上に下部キャップSi膜を形成する工程と、前記SiGe膜の形成温度よりも高い温度で前記下部キャップSi膜上に上部キャップSi膜を形成する工程とを含み、
前記不純物拡散層を形成した後、前記上部キャップSi膜及び前記不純物拡散層の上層に金属シリサイド層を形成する工程を含むことを特徴とする半導体装置の製造方法。 - 請求項10に記載の半導体装置の製造方法において、
前記上部キャップSi膜を530℃以上650℃以下の温度で形成することを特徴とする半導体装置の製造方法。 - 請求項10又は11に記載の半導体装置の製造方法において、
前記SiGe膜を450℃以上500℃未満の温度で形成することを特徴とする半導体装置の製造方法。
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JP2003307148A JP2005079310A (ja) | 2003-08-29 | 2003-08-29 | 半導体装置及びその製造方法 |
US10/925,990 US20050045938A1 (en) | 2003-08-29 | 2004-08-26 | Semiconductor device with silicon-germanium gate electrode and method for manufacturing thereof |
KR1020040067669A KR20050021337A (ko) | 2003-08-29 | 2004-08-27 | 반도체 장치 및 그 제조 방법 |
US11/360,398 US20060138518A1 (en) | 2003-08-29 | 2006-02-24 | Semiconductor device with silicon-germanium gate electrode and method for manufacturing thereof |
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FR2909221B1 (fr) * | 2006-11-29 | 2009-04-17 | Commissariat Energie Atomique | Procede de realisation d'un substrat mixte. |
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