JP2005072237A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2005072237A JP2005072237A JP2003299793A JP2003299793A JP2005072237A JP 2005072237 A JP2005072237 A JP 2005072237A JP 2003299793 A JP2003299793 A JP 2003299793A JP 2003299793 A JP2003299793 A JP 2003299793A JP 2005072237 A JP2005072237 A JP 2005072237A
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Abstract
【解決手段】 半導体基板1の主面のゲート絶縁膜4上に、多結晶シリコン膜5、タングステンシリサイド膜6および絶縁膜7を順に形成し、それらをパターニングして多結晶シリコン膜5およびタングステンシリサイド膜6の積層構造を有するゲート電極8を形成する。多結晶シリコン膜5のうち、多結晶シリコン領域5aは不純物をドープした多結晶シリコンにより形成し、多結晶シリコン領域5bはノンドープの多結晶シリコンにより形成する。また、タングステンシリサイド膜6の成膜時の抵抗率が1000μΩcm以上になるようにタングステンシリサイド膜6を堆積する。
【選択図】 図7
Description
本実施の形態の半導体装置の製造工程を図面を参照して説明する。図1および図2は、本発明の一実施の形態である半導体装置、例えばMISFET(Metal Insulator Semiconductor Field Effect Transistor)、の製造工程中の要部断面図である。
図15は、本発明の他の実施の形態である半導体装置の製造工程中の要部断面図である。図1までの製造工程は上記実施の形態1と同様であるので、ここではその説明は省略し、図1に続く製造工程について説明する。
図20は、本発明の他の実施の形態である半導体装置の製造工程中の要部断面図である。図1までの製造工程は上記実施の形態1と同様であるので、ここではその説明は省略し、図1に続く製造工程について説明する。
図25〜図29は、本発明の他の実施の形態である半導体装置の製造工程中の要部断面図である。本実施の形態では、フラッシュメモリを有する半導体装置(例えばフラッシュメモリ内蔵マイコン)の製造工程について説明する。
図30〜図33は、本発明の他の実施の形態である半導体装置の製造工程中の要部断面図である。本実施の形態では、DRAM(Dynamic Random Access Memory)の製造工程について説明する。なお、半導体基板の断面を示す図30〜図33の各図の左側部分はDRAMのメモリセルが形成される領域(メモリセル形成領域(MCFA))を示し、右側部分は論理回路等が形成される論理回路形成領域(LCFA)を示している。
図34〜図37は、本発明の他の実施の形態である半導体装置の製造工程中の要部断面図である。本実施の形態では、液晶表示装置(LCD:Liquid Crystal Display)を駆動するLCDドライバ回路が形成された半導体装置の製造工程について説明する。
本実施の形態では、半導体ウエハ(半導体基板)に種々の半導体素子または半導体集積回路を形成した後の検査工程について説明する。
2 素子分離領域
3 p型ウエル
4 ゲート絶縁膜
5 多結晶シリコン膜
5a 多結晶シリコン領域
5b 多結晶シリコン領域
5c 多結晶シリコン膜
5d 多結晶シリコン膜
5e 多結晶シリコン膜
5f 多結晶シリコン領域
5g 多結晶シリコン領域
5h 多結晶シリコン領域
6 タングステンシリサイド膜
7 絶縁膜
8 ゲート電極
8a ゲート電極
8b ゲート電極
10 酸化シリコン膜
11 n-型半導体領域
12 サイドウォール
13 n+型半導体領域
14 nチャネル型MISFET
15 絶縁膜
16 コンタクトホール
17 プラグ
17a 窒化チタン膜
18 配線
18a 高融点金属膜
18b 高融点金属窒化膜
18c 導電体膜(アルミニウム膜)
18d 高融点金属膜
18e 高融点金属窒化膜
21 ゲート電極
22 多結晶シリコン膜
23 タングステンシリサイド膜
24 酸化シリコン膜
25 タングステン酸化物
41 半導体基板
41A 領域
41B 領域
41C 領域
41D 領域
42 フィールド絶縁膜
43 n型アイソレーション領域
44 n型ウエル
45 p型ウエル
46 ゲート絶縁膜
47 多結晶シリコン膜
48 絶縁膜
49 ゲート絶縁膜
50 多結晶シリコン膜
51 タングステンシリサイド膜
52 酸化シリコン膜
54a ゲート電極
54b ゲート電極
54d ゲート電極
55 ゲート電極
55a 制御ゲート電極
55b 浮遊ゲート電極
61 n型半導体領域
62 p-型半導体領域
63 n-型半導体領域
64 サイドウォールスペーサ
65 p+型半導体領域
66 n+型半導体領域
70a 3.3V系nチャネル型MISFET
70b 3.3V系pチャネル型MISFET
70c MISFET
70d 高耐圧系昇圧nチャネル型MISFET
71 酸化シリコン膜
71a コンタクトホール
72 多結晶シリコン膜
73 BPSG膜
74 コンタクトホール
75 プラグ
76 配線
77 層間絶縁膜
78 スルーホール
79 プラグ
80 配線
101 半導体基板
102 素子分離領域
103 p型ウエル
104 n型ウエル
105 ゲート絶縁膜
106 多結晶シリコン膜
107 タングステンシリサイド膜
108 窒化シリコン膜
109a ゲート電極
109b ゲート電極
109c ゲート電極
111 n-型半導体領域
112 p-型半導体領域
113 窒化シリコン膜
114 n+型半導体領域
115 p+型半導体領域
117a pチャネル型MISFET
117b nチャネル型MISFET
117c 情報転送用MISFET
120 酸化シリコン膜
121a コンタクトホール
121b コンタクトホール
122 n+型半導体領域
123 プラグ
124 酸化シリコン膜
125 コンタクトホール
130 配線
131 酸化シリコン膜
132 スルーホール
133 プラグ
140 窒化シリコン膜
141 酸化シリコン膜
142 溝
143 多結晶シリコン膜
144 酸化タンタル膜
145 窒化チタン膜
150 キャパシタ
151 酸化シリコン膜
152 スルーホール
153 プラグ
154 配線
171 半導体基板
171A 領域
171B 領域
171C 領域
171D 領域
171E 領域
171F 領域
172 フィールド絶縁膜
173 n型アイソレーション領域
174 p型ウエル
175 p型半導体領域
176 n型半導体領域
177 n型ウエル
178 p型ウエル
181 ゲート絶縁膜
183 多結晶シリコン膜
185e ゲート電極
185f ゲート電極
191 ゲート絶縁膜
192 多結晶シリコン膜
193 タングステンシリサイド膜
195a ゲート電極
195b ゲート電極
195c ゲート電極
195d ゲート電極
196 n-型半導体領域
197 p-型半導体領域
198 サイドウォールスペーサ
199 n+型半導体領域
200 p+型半導体領域
201a 3V系nチャネル型MISFET
201b 3V系pチャネル型MISFET
201c 5V系nチャネル型MISFET
201d 5V系pチャネル型MISFET
201e 48V系nチャネル型MISFET
201f 48V系pチャネル型MISFET
202 絶縁膜
203 コンタクトホール
204 プラグ
205 配線
Claims (25)
- (a)半導体基板を準備する工程、
(b)前記半導体基板上に絶縁膜を形成する工程、
(c)前記絶縁膜上に、多結晶シリコン膜を形成する工程、
(d)前記多結晶シリコン膜上に金属シリサイド膜を形成する工程、
(e)前記金属シリサイド膜および前記多結晶シリコン膜をパターニングする工程、
(f)前記(e)工程後に、熱処理を行う工程、
を有し、
前記(c)工程では、前記多結晶シリコン膜の上面近傍の第1領域における不純物濃度が、前記第1領域よりも内部側の第2領域における不純物濃度よりも低くなるように、前記多結晶シリコン膜を形成し、
前記(d)工程で形成された前記金属シリサイド膜の抵抗率は1000μΩcm以上であり、前記(f)工程の前記熱処理後の前記金属シリサイド膜の抵抗率は400μΩcm以下であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程の熱処理後の前記金属シリサイド膜の抵抗率は200〜300μΩcmの範囲内であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記金属シリサイド膜はタングステンシリサイド膜であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(e)工程では、パターニングされた前記金属シリサイド膜および前記多結晶シリコン膜を有するゲート電極が形成されることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程の前記熱処理は、酸素を含む雰囲気中で行われることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程の前記熱処理により、前記多結晶シリコン膜および前記金属シリサイド膜の露出面に酸化シリコンを含む膜が形成されることを特徴とする半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法は更に、
前記多結晶シリコン膜および前記金属シリサイド膜の側壁に、前記酸化シリコンを含む膜を介してサイドウォールスペーサを形成する工程を含むことを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記多結晶シリコン膜の前記第2領域は、不純物をドープした多結晶シリコンからなり、前記多結晶シリコン膜の前記第1領域は、ノンドープの多結晶シリコンからなることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第2領域よりも前記絶縁膜に近い前記多結晶シリコン膜の第3領域は、前記第2領域よりも不純物濃度の低い多結晶シリコン膜からなることを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記第3領域の多結晶シリコン膜は、ノンドープの多結晶シリコンからなることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記多結晶シリコン膜の前記第1領域の厚みは、前記多結晶シリコン膜の厚みの1〜6%の範囲内にあることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記半導体装置は、マイコン、フラッシュメモリ内蔵マイコン、DRAMまたはLCDドライバに用いられる半導体装置であり、
前記(f)工程後に、
(g)前記半導体基板を切断して半導体チップに分離する工程、
(h)前記半導体チップをパッケージ化する工程、
を更に有し、
前記(h)工程後には、パッケージ化された半導体装置に対してバーンインを行わないことを特徴とする半導体装置の製造方法。 - (a)半導体基板を準備する工程、
(b)前記半導体基板上に絶縁膜を形成する工程、
(c)前記絶縁膜上に、不純物を含む第1多結晶シリコン膜を形成する工程、
(d)前記第1多結晶シリコン膜上に、前記第1多結晶シリコン膜よりも不純物濃度が低い第2多結晶シリコン膜を形成する工程、
(e)前記第2多結晶シリコン膜上にy/x≧2となるようにWxSiy膜を形成する工程、
(f)前記WxSiy膜、前記第2多結晶シリコン膜および前記第1多結晶シリコン膜をパターニングする工程、
(g)前記(f)工程後に、熱処理を行う工程、
を有することを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(e)工程で形成された前記WxSiy膜の抵抗率は1000μΩcm以上であり、前記(g)工程の前記熱処理後の前記WxSiy膜の抵抗率は400μΩcm以下であることを特徴とする半導体装置の製造方法。 - 請求項14記載の半導体装置の製造方法において、
前記(g)工程の前記熱処理後の前記WxSiy膜の抵抗率は200〜300μΩcmの範囲内であることを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(f)工程では、パターニングされた前記WxSiy膜、前記第2多結晶シリコン膜および前記第1多結晶シリコン膜を有するゲート電極が形成されることを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(g)工程の前記熱処理は、酸素を含む雰囲気中で行われることを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(g)工程の前記熱処理により、前記第1多結晶シリコン膜、前記第2多結晶シリコン膜および前記WxSiy膜の露出面に酸化シリコンを含む膜が形成されることを特徴とする半導体装置の製造方法。 - 請求項18記載の半導体装置の製造方法は更に、
前記多結晶シリコン膜および前記WxSiy膜の側壁に、前記酸化シリコンを含む膜を介してサイドウォールスペーサを形成する工程を含むことを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記第1多結晶シリコン膜は、不純物をドープした多結晶シリコン膜であり、前記第2多結晶シリコン膜は、ノンドープの多結晶シリコン膜であることを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(b)工程後であって前記(c)工程前に、前記絶縁膜上に前記第1多結晶シリコン膜よりも不純物濃度が低い第3多結晶シリコン膜を形成する工程を有し、
前記(c)工程で、前記第1多結晶シリコン膜は前記第3多結晶シリコン膜を介して前記絶縁膜上に形成されることを特徴とする半導体装置の製造方法。 - 請求項21記載の半導体装置の製造方法において、
前記第3多結晶シリコン膜は、ノンドープの多結晶シリコンからなることを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記第1多結晶シリコン膜の厚みは、前記第1および第2多結晶シリコン膜の合計の厚みの1〜6%の範囲内にあることを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記半導体装置は、マイコン、フラッシュメモリ内蔵マイコン、DRAMまたはLCDドライバに用いられる半導体装置であり、
前記(g)工程後に、
(h)前記半導体基板を切断して半導体チップに分離する工程、
(i)前記半導体チップをパッケージ化する工程、
を更に有し、
前記(i)工程後には、パッケージ化された半導体装置に対してバーンインを行わないことを特徴とする半導体装置の製造方法。 - メモリセル選択用MISFETと、前記メモリセル選択用MISFETの上部に前記MISFETのソース/ドレイン領域に電気的に接続するビット線および情報蓄積用容量素子とを配置するメモリセルを備えたDRAMを有する半導体装置の製造方法であって、
(a)半導体基板を準備する工程、
(b)前記半導体基板上に絶縁膜を形成する工程、
(c)前記絶縁膜上に、多結晶シリコン膜を形成する工程、
(d)前記多結晶シリコン膜上に、金属シリサイド膜を形成する工程、
(e)前記金属シリサイド膜および前記多結晶シリコン膜をパターニングすることで前記MISFETのゲート電極を形成する工程、
(f)前記(e)工程後に、熱処理を行う工程、
(g)前記半導体基板に不純物をイオン注入することで、前記MISFETのソース/ドレイン領域を形成する工程、
を有し、
前記(c)工程では、前記多結晶シリコン膜のうち前記金属シリサイド膜に近い第1領域における不純物濃度が、前記第1領域よりも前記絶縁膜に近い第2領域における不純物濃度よりも低くなるように、前記多結晶シリコン膜を形成すること、および、
前記(d)工程で形成された前記金属シリサイド膜の抵抗率は1000μΩcm以上であり、前記(f)工程の前記熱処理後の前記金属シリサイド膜の抵抗率は400μΩcm以下であることを特徴とする半導体装置の製造方法。
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