JP2005026655A - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
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- JP2005026655A JP2005026655A JP2003413095A JP2003413095A JP2005026655A JP 2005026655 A JP2005026655 A JP 2005026655A JP 2003413095 A JP2003413095 A JP 2003413095A JP 2003413095 A JP2003413095 A JP 2003413095A JP 2005026655 A JP2005026655 A JP 2005026655A
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- polysilicon layer
- amorphous silicon
- silicon layer
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 229920005591 polysilicon Polymers 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 41
- 230000008569 process Effects 0.000 claims abstract description 26
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims description 17
- 238000002955 isolation Methods 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims description 2
- 238000001953 recrystallisation Methods 0.000 claims description 2
- 230000000630 rising effect Effects 0.000 claims description 2
- 230000003746 surface roughness Effects 0.000 abstract description 5
- 239000013078 crystal Substances 0.000 abstract description 4
- 239000010409 thin film Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 24
- 238000005530 etching Methods 0.000 description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 235000001892 vitamin D2 Nutrition 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Recrystallisation Techniques (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
【解決手段】半導体素子を形成するためのいろいろの要素が設けられた半導体基板上に非晶質シリコン層を形成する段階と、スパイク急速熱処理工程で非晶質シリコン層を先に結晶化させ、グレインサイズが小さく且つ均一な非晶質ポリシリコン層に形成する段階とを含む。
【選択図】図4
Description
202 トンネル酸化膜
203 非晶質シリコン層
204 結晶化されたシリコン層
205 パッド窒化膜
206 トレンチ
207 熱酸化膜
208 素子分離膜
209 ポリシリコン層
210 フローティングゲート
Claims (7)
- 半導体素子を形成するための複数種類の要素が設けられた半導体基板上に非晶質シリコン層を形成する段階と、
スパイク急速熱処理工程で前記非晶質シリコン層をあらかじめ結晶化させ、グレインサイズが小さく且つ均一に結晶化された非晶質ポリシリコン層に形成する段階とを含むことを特徴とする半導体素子の製造方法。 - 半導体基板上にトンネル酸化膜を形成する段階と、
前記トンネル酸化膜上に非晶質シリコン層を形成する段階と、
スパイク急速熱処理工程で前記非晶質シリコン層をあらかじめ結晶化させ、グレインサイズが小さく且つ均一に結晶化された非晶質ポリシリコン層に形成する段階と、
前記結晶化された非晶質ポリシリコン層上にパッド窒化膜を形成する段階と、
素子分離領域上の前記パッド窒化膜、前記結晶化された非晶質ポリシリコン層及び前記トンネル酸化膜を除去する段階と、
前記素子分離領域の前記半導体基板にトレンチを形成する段階と、
側壁酸化工程で前記トレンチの側壁及び底面に熱酸化膜を形成する段階と、
前記トレンチを絶縁物質で埋め込んで素子分離膜を形成する段階と、
全体上部にポリシリコン層を形成した後、前記素子分離膜上の前記ポリシリコン層を一部除去し、前記結晶化された非晶質ポリシリコン層及び前記ポリシリコン層からなるフローティングゲートを形成する段階とを含むことを特徴とする半導体素子の製造方法。 - 前記非晶質シリコン層がアンドープト(undoped)非晶質ポリシリコン層であることを特徴とする請求項1又は2記載の半導体素子の製造方法。
- 前記非晶質シリコン層が300℃以上、且つ600℃以下の温度で形成されることを特徴とする請求項1又は2記載の半導体素子の製造方法。
- 前記スパイク急速熱処理工程がN2ガス雰囲気中で1秒当り100℃以上、且つ300℃以下の昇温速度で瞬間加熱方式によって行われることを特徴とする請求項1又は2記載の半導体素子の製造方法。
- 前記スパイク急速熱処理は、900℃以上、且つ1050℃以下の温度で行われ、円柱状の構造で形成されたグレインサイズが600Åよりも小さくなるように熱処理条件が調節されることを特徴とする請求項1又は2記載の半導体素子の製造方法。
- 前記側壁酸化工程は、前記結晶化された非晶質ポリシリコン層の過多粒成長が発生する2次再結晶化を防止することが可能な温度で行われることを特徴とする請求項2記載の半導体素子の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030043621A KR100573480B1 (ko) | 2003-06-30 | 2003-06-30 | 반도체 소자의 제조 방법 |
Publications (1)
Publication Number | Publication Date |
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JP2005026655A true JP2005026655A (ja) | 2005-01-27 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2003413095A Pending JP2005026655A (ja) | 2003-06-30 | 2003-12-11 | 半導体素子の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6974747B2 (ja) |
JP (1) | JP2005026655A (ja) |
KR (1) | KR100573480B1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100539275B1 (ko) * | 2004-07-12 | 2005-12-27 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
US7115458B2 (en) * | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Gate coupling in floating-gate memory cells |
US7449743B2 (en) * | 2005-02-22 | 2008-11-11 | Intel Corporation | Control gate profile for flash technology |
KR100739988B1 (ko) * | 2006-06-28 | 2007-07-16 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 제조방법 |
US20080194093A1 (en) * | 2006-09-26 | 2008-08-14 | Hynix Semiconductor Inc. | Method for fabricating a nonvolatile memory device |
KR20080099463A (ko) * | 2007-05-09 | 2008-11-13 | 주식회사 하이닉스반도체 | 반도체 소자, 비휘발성 메모리 소자 및 그 제조방법 |
KR100914292B1 (ko) * | 2007-11-07 | 2009-08-27 | 주식회사 하이닉스반도체 | 실리콘 나노크리스탈을 갖는 전하트랩층 형성방법과, 이를이용한 불휘발성 메모리소자 및 그 제조방법 |
KR101098113B1 (ko) * | 2010-07-07 | 2011-12-26 | 주식회사 하이닉스반도체 | 반도체 소자의 형성방법 |
US8895435B2 (en) * | 2011-01-31 | 2014-11-25 | United Microelectronics Corp. | Polysilicon layer and method of forming the same |
KR101868630B1 (ko) * | 2011-02-14 | 2018-06-18 | 에스케이하이닉스 주식회사 | 원주 구조의 나노 입자를 갖는 반도체 소자의 게이트 및 그 제조방법 |
US10923503B2 (en) * | 2018-07-02 | 2021-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3156878B2 (ja) * | 1992-04-30 | 2001-04-16 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP2817645B2 (ja) * | 1995-01-25 | 1998-10-30 | 日本電気株式会社 | 半導体装置の製造方法 |
KR19980055759A (ko) | 1996-12-28 | 1998-09-25 | 김영환 | 폴리실리콘층 형성 방법 |
JP3727449B2 (ja) * | 1997-09-30 | 2005-12-14 | シャープ株式会社 | 半導体ナノ結晶の製造方法 |
KR100456315B1 (ko) | 1998-12-22 | 2005-01-15 | 주식회사 하이닉스반도체 | 반도체소자의 게이트전극 형성방법 |
KR100537277B1 (ko) * | 2002-11-27 | 2005-12-19 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
-
2003
- 2003-06-30 KR KR1020030043621A patent/KR100573480B1/ko active IP Right Grant
- 2003-12-11 JP JP2003413095A patent/JP2005026655A/ja active Pending
- 2003-12-18 US US10/740,089 patent/US6974747B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6974747B2 (en) | 2005-12-13 |
KR20050002252A (ko) | 2005-01-07 |
US20040266215A1 (en) | 2004-12-30 |
KR100573480B1 (ko) | 2006-04-24 |
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