JP2004535065A - 多孔質材料上のＳｉＣ：Ｈ蒸着によって改良された金属バリア挙動 - Google Patents

多孔質材料上のＳｉＣ：Ｈ蒸着によって改良された金属バリア挙動 Download PDF

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Publication number
JP2004535065A
JP2004535065A JP2003511305A JP2003511305A JP2004535065A JP 2004535065 A JP2004535065 A JP 2004535065A JP 2003511305 A JP2003511305 A JP 2003511305A JP 2003511305 A JP2003511305 A JP 2003511305A JP 2004535065 A JP2004535065 A JP 2004535065A
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Japan
Prior art keywords
value
atomic
dielectric layer
sealing
integrated circuit
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Pending
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JP2003511305A
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Japanese (ja)
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JP2004535065A5 (https=
Inventor
メイネン、ヘルマン
ウィードナー、ウィリアム・ケネス
イアコピ、フランチェスカ
マルウィトル、ステファン
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Dow Silicones Corp
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Dow Corning Corp
Dow Silicones Corp
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Publication of JP2004535065A publication Critical patent/JP2004535065A/ja
Publication of JP2004535065A5 publication Critical patent/JP2004535065A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Laminated Bodies (AREA)
JP2003511305A 2001-07-02 2002-06-25 多孔質材料上のＳｉＣ：Ｈ蒸着によって改良された金属バリア挙動 Pending JP2004535065A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30246901P 2001-07-02 2001-07-02
PCT/US2002/020704 WO2003005438A2 (en) 2001-07-02 2002-06-25 Improved metal barrier behavior by sic:h deposition on porous materials

Publications (2)

Publication Number Publication Date
JP2004535065A true JP2004535065A (ja) 2004-11-18
JP2004535065A5 JP2004535065A5 (https=) 2006-01-05

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JP2003511305A Pending JP2004535065A (ja) 2001-07-02 2002-06-25 多孔質材料上のＳｉＣ：Ｈ蒸着によって改良された金属バリア挙動

Country Status (5)

Country Link
US (1) US6541842B2 (https=)
JP (1) JP2004535065A (https=)
KR (1) KR100847926B1 (https=)
CN (1) CN1596466A (https=)
WO (1) WO2003005438A2 (https=)

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* Cited by examiner, † Cited by third party
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JP2006190872A (ja) * 2005-01-07 2006-07-20 Fujitsu Ltd 半導体装置の製造方法
JP2006216541A (ja) * 2005-01-21 2006-08-17 Internatl Business Mach Corp <Ibm> 誘電体材料、相互接続構造、電子構造、電子センシング構造および該製作方法（改良された靭性および改良されたＳｉ−Ｃ結合を有するＳｉＣＯＨ誘電体材料、該誘電体材料を含む半導体デバイスおよび該誘電体材料の製作方法）
JP2007088017A (ja) * 2005-09-20 2007-04-05 National Institute Of Advanced Industrial & Technology 有機絶縁膜とその作製方法，及び有機絶縁膜を用いた半導体装置
JP2008520100A (ja) * 2004-11-12 2008-06-12 アクセリス テクノロジーズ インコーポレーテッド 多孔性低ｋ誘電体フィルムの紫外線に補助された細孔シーリング
JP2010073933A (ja) * 2008-09-19 2010-04-02 Fujitsu Microelectronics Ltd 半導体装置の製造方法及び半導体装置
JP2012506147A (ja) * 2008-10-20 2012-03-08 ダウ コーニング コーポレーション Ｃｖｄ前駆体
JP2020518725A (ja) * 2017-06-02 2020-06-25 ノースロップ グラマン システムズ コーポレイションＮｏｒｔｈｒｏｐ Ｇｒｕｍｍａｎ Ｓｙｓｔｅｍｓ Ｃｏｒｐｏｒａｔｉｏｎ 超伝導体相互接続のための堆積方法

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008520100A (ja) * 2004-11-12 2008-06-12 アクセリス テクノロジーズ インコーポレーテッド 多孔性低ｋ誘電体フィルムの紫外線に補助された細孔シーリング
JP2006190872A (ja) * 2005-01-07 2006-07-20 Fujitsu Ltd 半導体装置の製造方法
JP2006216541A (ja) * 2005-01-21 2006-08-17 Internatl Business Mach Corp <Ibm> 誘電体材料、相互接続構造、電子構造、電子センシング構造および該製作方法（改良された靭性および改良されたＳｉ−Ｃ結合を有するＳｉＣＯＨ誘電体材料、該誘電体材料を含む半導体デバイスおよび該誘電体材料の製作方法）
JP2007088017A (ja) * 2005-09-20 2007-04-05 National Institute Of Advanced Industrial & Technology 有機絶縁膜とその作製方法，及び有機絶縁膜を用いた半導体装置
JP2010073933A (ja) * 2008-09-19 2010-04-02 Fujitsu Microelectronics Ltd 半導体装置の製造方法及び半導体装置
JP2012506147A (ja) * 2008-10-20 2012-03-08 ダウ コーニング コーポレーション Ｃｖｄ前駆体
JP2014017502A (ja) * 2008-10-20 2014-01-30 Dow Corning Corp Ｃｖｄ前駆体
JP2020518725A (ja) * 2017-06-02 2020-06-25 ノースロップ グラマン システムズ コーポレイションＮｏｒｔｈｒｏｐ Ｇｒｕｍｍａｎ Ｓｙｓｔｅｍｓ Ｃｏｒｐｏｒａｔｉｏｎ 超伝導体相互接続のための堆積方法
JP7038139B2 (ja) 2017-06-02 2022-03-17 ノースロップ グラマン システムズ コーポレーション 超伝導体相互接続のための堆積方法

Also Published As

Publication number Publication date
US6541842B2 (en) 2003-04-01
KR20040032119A (ko) 2004-04-14
WO2003005438A3 (en) 2003-05-01
WO2003005438A2 (en) 2003-01-16
US20030001282A1 (en) 2003-01-02
CN1596466A (zh) 2005-03-16
KR100847926B1 (ko) 2008-07-22

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