JP5372323B2 - 界面ラフネス緩和膜、これを用いた配線層および半導体装置ならびに半導体装置の製造方法 - Google Patents
界面ラフネス緩和膜、これを用いた配線層および半導体装置ならびに半導体装置の製造方法 Download PDFInfo
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- JP5372323B2 JP5372323B2 JP2006349409A JP2006349409A JP5372323B2 JP 5372323 B2 JP5372323 B2 JP 5372323B2 JP 2006349409 A JP2006349409 A JP 2006349409A JP 2006349409 A JP2006349409 A JP 2006349409A JP 5372323 B2 JP5372323 B2 JP 5372323B2
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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Description
Si(OR7)4・・・・・・式(1)
R1Si(OR8)3・・・・・式(2)
R2R3Si(OR9)2・・・式(3)
R4R5R6SiOR10・・・式(4)
R1' x(OR2' (4-x))Si−[R7'−SiR5'R6']n−R8'−SiR3' y(OR4' (4-y))・・・・・・式(1’)
(式1〜4中のR1〜R10は、互いに独立に、炭素数1〜20のアルキル基、炭素数2〜20のアルケニル基、アルキニル基、アルキルカルボニル基、アルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜20のアリール基からなる群から選ばれた基である。また、式1’中のR1'〜R6'は、互いに独立に、水素、炭素数1〜20のアルキル基、炭素数2〜20のアルケニル基、アルキニル基、アルキルカルボニル基、アルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜20のアリール基からなる群から選ばれた基である。R7'、R8'は、互いに独立に、炭素数1〜20の炭化水素基である。nは0〜18の整数、x、yは、互いに独立に、0〜4の整数である。)、とりわけ、前記式1〜4中のR1〜R10が、互いに独立に、炭素数1〜3のアルキル基、炭素数2〜4のアルケニル基、アルキニル基およびアルキルカルボニル基、炭素数3〜6のアルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜10のアリール基からなる群から選ばれた基であり、前記式1’中のR1'〜R6'が、互いに独立に、炭素数1〜3のアルキル基、炭素数2〜4のアルケニル基、アルキニル基およびアルキルカルボニル基、炭素数3〜6のアルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜10のアリール基からなる群から選ばれた基であり、R7'、R8'は、互いに独立に、炭素数1〜3の炭化水素基であること、使用される状態におけるpHが4〜10であること、が好ましい。
Si(OR11)4・・・・・・式(5)
X1Si(OR12)3・・・・式(6)
X2X3Si(OR13)2・・・式(7)
X4X5X6SiOR14・・・式(8)
(式(5)〜(8)中、X1〜X6は、互いに独立に、水素原子、フッ素原子、炭素数1〜8のアルキル基、フッ素置換アルキル基、アリール基およびビニル基からなる群から選ばれる。R11〜R14は互いに独立に、炭素数1〜20のアルキル基、炭素数2〜20のアルケニル基、アルキニル基、アルキルカルボニル基、アルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜20のアリール基からなる群から選ばれた基である。)
が好ましい。
X1Si(OR12)3 式(6)
X2X3Si(OR13)2・・・式(7)
X4X5X6SiOR14・・・式(8)
(式(5)〜(8)中、X1〜X6は、互いに独立に、水素原子、フッ素原子、炭素数1〜8のアルキル基、フッ素置換アルキル基、アリール基およびビニル基からなる群から選ばれる。R11〜R14は互いに独立に、炭素数1〜20のアルキル基、炭素数2〜20のアルケニル基、アルキニル基、アルキルカルボニル基、アルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜20のアリール基からなる群から選ばれた基である。)
このようにして得られる低誘電率膜は同等の誘電率を持つ他の低誘電率膜と比較して機械的強度・絶縁性・信頼性に優れていることが多く、絶縁性・信頼性のより高い配線層(LSI配線層等)の形成に寄与し得る。
R1Si(OR8)3・・・・・式(2)
R2R3Si(OR9)2・・・式(3)
R4R5R6SiOR10・・・式(4)
R1' x(OR2' (4-x))Si−[R7'−SiR5'R6']n−R8'−SiR3' y(OR4' (4-y))・・・・・・式(1’)
(式1〜4中のR1〜R10は、互いに独立に、炭素数1〜20のアルキル基、炭素数2〜20のアルケニル基、アルキニル基、アルキルカルボニル基、アルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜20のアリール基からなる群から選ばれた基である。また、式1’中のR1'〜R6'は、互いに独立に、水素、炭素数1〜20のアルキル基、炭素数2〜20のアルケニル基、アルキニル基、アルキルカルボニル基、アルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜20のアリール基からなる群から選ばれた基である。R7'、R8'は、互いに独立に、炭素数1〜20の炭化水素基である。nは0〜18の整数、x、yは、互いに独立に、0〜4の整数である。)
これらの剤は、容易に、加水分解物、縮合物およびそれらの混合物に変性することができ。これらの剤や、加水分解物、縮合物およびそれらの混合物を使用することにより、上記効果を与える界面ラフネス緩和膜を容易に作製することができる。
(I)半導体装置の配線溝やビア孔をエッチングで形成する工程
(II)次いで、界面ラフネス緩和膜を形成する工程
(III)次いで、バリアメタル層を形成する工程
を含むように用いると、実際半導体装置の製造に好適に応用でき、効果的である。具体的には、エッチングによる配線溝のラフネスを低減することができ、配線間のリークがより少なく、またより信頼性の高いLSI配線層を形成可能になる。
比誘電率2.5のケイ素含有化合物よりなる塗布型低誘電率絶縁材料を低抵抗基板上に250nmの膜厚になるようにスピンコートし、250℃,3分でプリベークを行った後、N2雰囲気の電気炉にて、400℃,30分の条件でキュアを行った。その後、200nmの深さになるよう全面エッチングを行った。
図1〜10に本発明に関わる多層配線実施例の作製法を示す。まず、素子間分離膜2で分離され、ソース拡散層5aとドレイン拡散層5bとサイドウォール絶縁膜3とを有するゲート電極4を形成したトランンジスタ層を形成したシリコンウェハ1(ステップ1)に、層間絶縁膜6(リンガラス)およびストッパ膜7を形成し(ステップ2)、電極取り出し用のコンタクトホール21を形成した(ステップ3)。
実施例2において、界面ラフネス緩和層12、20を実施例1のサンプル6を用いて作製し、他はまったく同様にして3層配線を形成した。試作した多層配線の櫛歯パターンを用いてTDDB測定を行ったところ、ブレークダウンまでの時間のメジアンは426秒であった。
実施例2において、界面ラフネス緩和層12、20を実施例1のサンプル7を用いて作製し、他はまったく同様にして3層配線を形成した。試作した多層配線の櫛歯パターンを用いてTDDB測定を行ったところ、ブレークダウンまでの時間のメジアンは409秒であった。
実施例2において、界面ラフネス緩和膜12、20を形成せず、他は全く同様にして3層配線を形成した。試作した多層配線の櫛歯パターンを用いてEM測定を行ったところ、ブレークダウンまでの時間のメジアンは58秒であった。
絶縁膜と接触した界面ラフネス緩和膜であって、その反対側の面で配線とも接触し、当該絶縁膜と当該界面ラフネス緩和膜との間の界面ラフネスより、当該配線と当該界面ラフネス緩和膜との間の界面ラフネスの方が小さい界面ラフネス緩和膜。
前記界面ラフネス緩和膜が、前記絶縁膜の表面粗化を伴う処理の後に設けられたものである、付記1に記載の界面ラフネス緩和膜。
前記界面ラフネス緩和膜が、
ケイ素を含み、
更に、酸素とケイ素との少なくともいずれか一方を含む、
付記1または2に記載の界面ラフネス緩和膜。
前記界面ラフネス緩和膜が、SiO骨格とSiC骨格との少なくともいずれか一方を有する、付記1〜3のいずれかに記載の界面ラフネス緩和膜。
前記絶縁膜が比誘電率2.7以下の低誘電率絶縁膜である、付記1〜4のいずれかに記載の界面ラフネス緩和膜。
付記1〜5のいずれかに記載の界面ラフネス緩和膜を含んでなる配線層。
付記1〜5のいずれかに記載の界面ラフネス緩和膜を含んでなる半導体装置。
絶縁膜と接触した界面ラフネス緩和膜であって、その反対側の面で配線とも接触し、当該絶縁膜と当該界面ラフネス緩和膜との間の界面ラフネスより、当該配線と当該界面ラフネス緩和膜との間の界面ラフネスの方が小さい界面ラフネス緩和膜に用いられる界面ラフネス緩和膜形成材料であって、平均分子量が1000以下である条件と、一分子内に含まれるケイ素原子の数が20以下である条件との少なくともいずれか一つを満たすケイ素化合物を含有してなる界面ラフネス緩和膜形成材料。
前記界面ラフネス緩和膜が、前記絶縁膜の表面粗化を伴う処理の後に設けられたものである、付記8に記載の界面ラフネス緩和膜形成材料。
前記ケイ素化合物が、オルガノシラン、オルガノシランの加水分解物および縮合物ならびにそれらの混合物からなる群から選ばれたものである、付記8または9に記載の界面ラフネス緩和膜形成材料。
前記オルガノシランを加水分解して得られる生成物中に含まれる成分と同一物質である溶媒を含む、付記10に記載の界面ラフネス緩和膜形成材料。
前記オルガノシランが下記(1)〜(4),(1’)のいずれかの式で表される、付記11または12に記載の界面ラフネス緩和膜形成材料。
R1Si(OR8)3・・・・・式(2)
R2R3Si(OR9)2・・・式(3)
R4R5R6SiOR10・・・式(4)
R1' x(OR2' (4-x))Si−[R7'−SiR5'R6']n−R8'−SiR3' y(OR4' (4-y))・・・・・・式(1’)
(式1〜4中のR1〜R10は、互いに独立に、炭素数1〜20のアルキル基、炭素数2〜20のアルケニル基、アルキニル基、アルキルカルボニル基、アルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜20のアリール基からなる群から選ばれた基である。また、式1’中のR1'〜R6'は、互いに独立に、水素、炭素数1〜20のアルキル基、炭素数2〜20のアルケニル基、アルキニル基、アルキルカルボニル基、アルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜20のアリール基からなる群から選ばれた基である。R7'、R8'は、互いに独立に、炭素数1〜20の炭化水素基である。nは0〜18の整数、x、yは、互いに独立に、0〜4の整数である。)
(付記13)
付記8〜12のいずれかに記載の界面ラフネス緩和膜形成材料を用いて作製された、付記1〜5のいずれかに記載の界面ラフネス緩和膜。
付記8〜12のいずれかに記載の界面ラフネス緩和膜形成材料を用いて作製された配線層。
付記8〜12のいずれかに記載の界面ラフネス緩和膜形成材料を用いて作製された半導体装置。
半導体装置上の絶縁膜に接して付記8〜12のいずれかに記載の界面ラフネス緩和膜形成材料を塗布することと、
その後当該半導体装置を80℃〜500℃で0.5〜180分間加熱して界面ラフネス緩和膜を形成することと
を含む半導体装置の製造方法。
前記絶縁膜が表面粗化を伴う処理を受けたものである、付記16に記載の半導体装置の製造方法。
前記塗布がスピンコーティングまたはベーパー処理である、付記16また17に記載の半導体装置の製造方法。
前記絶縁膜が、下記式(5)〜(8)で表されるシラン化合物を単独または組み合わせ、テトラアルキルアンモニウムハイドロオキサイドの存在下、加水分解して得られる有機ケイ素化合物を含む液状組成物を、被加工基材上に塗布し、当該被加工基材上に塗布された液状組成物からなる被膜を80℃以上350℃以下の温度で加熱処理し、当該加熱処理により加熱された被膜を350℃より高く450℃以下の温度で焼成することを含んでなる処理により得られたものである、付記16〜18のいずれかに記載の半導体装置の製造方法。
X1Si(OR12)3・・・・式(6)
X2X3Si(OR13)2・・・式(7)
X4X5X6SiOR14・・・式(8)
(式(5)〜(8)中、X1〜X6は、互いに独立に、水素原子、フッ素原子、炭素数1〜8のアルキル基、フッ素置換アルキル基、アリール基およびビニル基からなる群から選ばれる。R11〜R14は互いに独立に、炭素数1〜20のアルキル基、炭素数2〜20のアルケニル基、アルキニル基、アルキルカルボニル基、アルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜20のアリール基からなる群から選ばれた基である。)
(付記20)
付記16〜19のいずれかに記載の製造法を用いて製造された半導体装置。
2 素子間分離膜
3 サイドウォール絶縁膜
4 ゲート電極
5a ソース拡散層
5b ドレイン拡散層
6 層間絶縁膜
7 ストッパ膜
8 TiN
9 導体プラグ
10 低誘電率被膜(配線分離絶縁膜)
11 TEOS−SiO2膜
12 界面ラフネス緩和膜
13 SiOC膜
14 SiN膜
15 低誘電率絶縁膜
16 TEOS−SiO2膜
17 Cu層
18 Cu層
19 キャップ層
20 界面ラフネス緩和膜
21 コンタクトホール
22 配線溝
23 シード層
24 配線層
25 ビア
26 配線溝
27 シード層
28 ビア
29 配線層
30 ビア穴
111 配線
112 バリアメタル層
113 界面ラフネス緩和膜
114 絶縁膜
Claims (6)
- 絶縁膜と接触した界面ラフネス緩和膜であって、その反対側の面で配線とも接触し、当該絶縁膜と当該界面ラフネス緩和膜との間の界面ラフネスより、当該配線と当該界面ラフネス緩和膜との間の界面ラフネスの方が小さく、
平均分子量が1000以下である条件と、一分子内に含まれるケイ素原子の数が20以下である条件との少なくともいずれか一つを満たし、下記(1’)の式で表されるオルガノシランを含有してなる界面ラフネス緩和膜形成材料を用いて作製された界面ラフネス緩和膜
R 1' x (OR 2' ) (3-x) Si−[R 7' −SiR 5' R 6' ] n −R 8' −SiR 3' y (OR 4' ) (3-y) ・・・・・・式(1’)
(式1’中のR 1' 〜R 6' は、互いに独立に、水素、炭素数1〜20のアルキル基、炭素数2〜20のアルケニル基、アルキニル基、アルキルカルボニル基、アルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜20のアリール基からなる群から選ばれた基である。R 7' 、R 8' は、互いに独立に、炭素数1〜20の炭化水素基である。nは1〜18の整数、x、yは、互いに独立に、0〜2の整数である。)。 - 前記界面ラフネス緩和膜形成材料が、更に、下記(1)〜(4)のいずれかの式で表されるオルガノシランも含有する、請求項1に記載の界面ラフネス緩和膜。
Si(OR 7 ) 4 ・・・・・・式(1)
R 1 Si(OR 8 ) 3 ・・・・・式(2)
R 2 R 3 Si(OR 9 ) 2 ・・・式(3)
R 4 R 5 R 6 SiOR 10 ・・・式(4)
(式1〜4中のR 1 〜R 10 は、互いに独立に、炭素数1〜20のアルキル基、炭素数2〜20のアルケニル基、アルキニル基、アルキルカルボニル基、アルケニルアルキル基およびアルキニルアルキル基ならびに炭素数6〜20のアリール基からなる群から選ばれた基である。) - 請求項1または2に記載の界面ラフネス緩和膜を含んでなる配線層。
- 請求項1または2に記載の界面ラフネス緩和膜を含んでなる半導体装置。
- 半導体装置上の絶縁膜に接して請求項1または2に記載の界面ラフネス緩和膜形成材料を塗布することと、
その後当該半導体装置を80℃〜500℃で0.5〜180分間加熱して、請求項1または2に記載の界面ラフネス緩和膜を形成することと
を含む半導体装置の製造方法。 - 請求項5に記載の製造法を用いて製造された半導体装置。
Priority Applications (5)
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JP2006349409A JP5372323B2 (ja) | 2006-03-29 | 2006-12-26 | 界面ラフネス緩和膜、これを用いた配線層および半導体装置ならびに半導体装置の製造方法 |
EP17170157.6A EP3240017A1 (en) | 2006-03-29 | 2007-03-21 | Method for forming a roughness reducing film at an interface and corresponding semiconductor device |
EP07005824A EP1840949A3 (en) | 2006-03-29 | 2007-03-21 | Roughness reducing film at an interface between a wiring line and a dielectric, materials for forming the roughness reducing film, and method for manufacturing a semiconductor device |
US11/727,001 US7928536B2 (en) | 2006-03-29 | 2007-03-23 | Roughness reducing film at interface, materials for forming roughness reducing film at interface, wiring layer and semiconductor device using the same, and method for manufacturing semiconductor device |
KR1020070029755A KR100875695B1 (ko) | 2006-03-29 | 2007-03-27 | 계면 러프니스 완화막, 계면 러프니스 완화막 형성 재료,이들을 이용한 배선층 및 반도체 장치, 및 반도체 장치의제조 방법 |
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JP2006349409A JP5372323B2 (ja) | 2006-03-29 | 2006-12-26 | 界面ラフネス緩和膜、これを用いた配線層および半導体装置ならびに半導体装置の製造方法 |
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US (1) | US7928536B2 (ja) |
EP (2) | EP3240017A1 (ja) |
JP (1) | JP5372323B2 (ja) |
KR (1) | KR100875695B1 (ja) |
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JP5119832B2 (ja) | 2007-09-27 | 2013-01-16 | 富士通株式会社 | 界面ラフネス緩和膜、配線層、半導体装置および半導体装置の製造方法 |
JP2010114255A (ja) * | 2008-11-06 | 2010-05-20 | Toshiba Corp | 半導体装置の製造方法 |
WO2010064306A1 (ja) | 2008-12-03 | 2010-06-10 | 富士通株式会社 | 半導体装置の製造方法 |
US9219206B2 (en) * | 2010-01-19 | 2015-12-22 | Lg Innotek Co., Ltd. | Package and manufacturing method of the same |
US10541172B2 (en) | 2016-08-24 | 2020-01-21 | International Business Machines Corporation | Semiconductor device with reduced contact resistance |
KR20210018669A (ko) * | 2019-08-08 | 2021-02-18 | 삼성전자주식회사 | 비아 및 배선을 포함하는 반도체 소자 |
KR20210079034A (ko) * | 2019-12-19 | 2021-06-29 | 삼성전기주식회사 | 전자부품 내장기판 |
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JPS6415952A (en) * | 1987-07-10 | 1989-01-19 | Nec Corp | Manufacture of semiconductor device |
JPH06267946A (ja) | 1993-03-16 | 1994-09-22 | Kawasaki Steel Corp | 金属膜の選択形成方法 |
JP2000109679A (ja) * | 1998-10-06 | 2000-04-18 | Sony Corp | 低誘電率絶縁膜用樹脂組成物、低誘電率絶縁膜形成方法及び半導体装置の製造方法 |
US6770572B1 (en) | 1999-01-26 | 2004-08-03 | Alliedsignal Inc. | Use of multifunctional si-based oligomer/polymer for the surface modification of nanoporous silica films |
JP4195773B2 (ja) * | 2000-04-10 | 2008-12-10 | Jsr株式会社 | 層間絶縁膜形成用組成物、層間絶縁膜の形成方法およびシリカ系層間絶縁膜 |
AU2001266998A1 (en) | 2000-06-23 | 2002-01-08 | Honeywell International, Inc. | Method to restore hydrophobicity in dielectric films and materials |
US6586334B2 (en) * | 2000-11-09 | 2003-07-01 | Texas Instruments Incorporated | Reducing copper line resistivity by smoothing trench and via sidewalls |
WO2002071476A2 (en) * | 2001-03-06 | 2002-09-12 | Advanced Micro Devices, Inc. | Method of forming conductive interconnections in porous insulating films and associated device |
US6541842B2 (en) | 2001-07-02 | 2003-04-01 | Dow Corning Corporation | Metal barrier behavior by SiC:H deposition on porous materials |
US20040077757A1 (en) * | 2002-02-06 | 2004-04-22 | Toru Araki | Coating composition for use in producing an insulating thin film |
US7442756B2 (en) * | 2002-06-20 | 2008-10-28 | Infineon Technologies Ag | Polymer for sealing porous materials during chip production |
JP4261297B2 (ja) | 2002-09-09 | 2009-04-30 | 三井化学株式会社 | 多孔質フィルムの改質方法、改質された多孔質フィルム及びその用途 |
US20040109950A1 (en) * | 2002-09-13 | 2004-06-10 | Shipley Company, L.L.C. | Dielectric materials |
JP4081751B2 (ja) * | 2002-12-11 | 2008-04-30 | ソニー株式会社 | 配線構造の製造方法 |
US7268075B2 (en) | 2003-05-16 | 2007-09-11 | Intel Corporation | Method to reduce the copper line roughness for increased electrical conductivity of narrow interconnects (<100nm) |
US7057287B2 (en) * | 2003-08-21 | 2006-06-06 | International Business Machines Corporation | Dual damascene integration of ultra low dielectric constant porous materials |
US7244674B2 (en) * | 2004-04-27 | 2007-07-17 | Agency For Science Technology And Research | Process of forming a composite diffusion barrier in copper/organic low-k damascene technology |
JP4540504B2 (ja) | 2005-03-03 | 2010-09-08 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US8241708B2 (en) * | 2005-03-09 | 2012-08-14 | Micron Technology, Inc. | Formation of insulator oxide films with acid or base catalyzed hydrolysis of alkoxides in supercritical carbon dioxide |
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2006
- 2006-12-26 JP JP2006349409A patent/JP5372323B2/ja active Active
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2007
- 2007-03-21 EP EP17170157.6A patent/EP3240017A1/en not_active Withdrawn
- 2007-03-21 EP EP07005824A patent/EP1840949A3/en not_active Withdrawn
- 2007-03-23 US US11/727,001 patent/US7928536B2/en active Active
- 2007-03-27 KR KR1020070029755A patent/KR100875695B1/ko active IP Right Grant
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EP1840949A3 (en) | 2007-11-14 |
US7928536B2 (en) | 2011-04-19 |
JP2007294854A (ja) | 2007-11-08 |
EP3240017A1 (en) | 2017-11-01 |
KR100875695B1 (ko) | 2008-12-23 |
US20070232075A1 (en) | 2007-10-04 |
KR20070098577A (ko) | 2007-10-05 |
EP1840949A2 (en) | 2007-10-03 |
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